Patents by Inventor Deep Narula

Deep Narula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250334635
    Abstract: An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 30, 2025
    Inventors: Deep Narula, Akshat Gupta, Amitesh Khandelwal, Uzi Zangi, Noga Dayag, Himanshu Atri