Patents by Inventor Deepa Palamadai Sundar

Deepa Palamadai Sundar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11823367
    Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: November 21, 2023
    Assignee: Meta Platforms, Inc.
    Inventors: Deepa Palamadai Sundar, Xing Cindy Chen, Visalakshi Vaduganathan, Harikrishna Madadi Reddy
  • Publication number: 20220286697
    Abstract: The disclosed computer-implemented method may include receiving video data to be encoded, determining pixels for a first transform unit (TU) of a first prediction unit (PU) of a square shape of the video data, storing the pixels in a buffer, performing intra-prediction for a second PU by reusing the stored pixels for a second TU of the second PU, and encoding the video data based on the intra-prediction. A system may include a video encoder and/or a tape holder apparatus. The tape holder apparatus may include a cubical tape holder to hold multiple tape cartridges in a stack, wherein a tape cartridge may be inserted into a top of the cubical tape holder. The tape holder apparatus may include a handle and a horizontal slot enabling a single tape cartridge to be pushed out from a bottom of the stack. Various other methods, systems, and apparatuses are also disclosed.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Yunqing Chen, Rohan Prakash Mallya, Lei Feng, Deepa Palamadai Sundar, Visalakshi Vaduganathan, Harikrishna Madadi Reddy, Jose Gallegos, Caleb Cotton, Erik Schaeffer, Jason Odom
  • Publication number: 20220046318
    Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Inventors: Deepa Palamadai Sundar, Xing Cindy Chen, Visalakshi Vaduganathan, Harikrishna Madadi Reddy
  • Publication number: 20220044386
    Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes an interface configured to receive pixel data of a frame of a video being analyzed for quality metric determination and a kernel configured to compute a video quality metric for the received pixel data using a fixed-point hardware approximation of a floating-point based algorithm associated with the video quality metric.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Inventors: Deepa Palamadai Sundar, Xing Cindy Chen, Hsiao-Chiang Chuang, Visalakshi Vaduganathan, Harikrishna Madadi Reddy
  • Publication number: 20220046254
    Abstract: Techniques to optimize memory reads when computing a video quality metric are disclosed. In some embodiments, an application-specific integrated circuit for computing video quality metrics includes a set of caches configured to store neighbor pixel data for edge width searches of pixels comprising a frame of a video being analyzed for a video quality metric and a kernel configured to receive corresponding neighbor pixel data for pixels comprising a current processing block of the frame from a subset of the set of caches and simultaneously perform edge width searches for pixels comprising the current processing block to determine corresponding pixel edge width values used for computing the video quality metric.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Inventors: Deepa Palamadai Sundar, Visalakshi Vaduganathan, Harikrishna Madadi Reddy
  • Publication number: 20220046257
    Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a first scaling unit configured to scale a resolution of at least a portion of a reference frame of a video, a second scaling unit configured to scale a resolution of at least a portion of a distorted frame of a transcoded version of the video, and a kernel configured to compute a video quality metric for the distorted frame with respect to the reference frame using at least a first scaled output of the first scaling unit or a second scaled output of the second scaling unit.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Inventors: Deepa Palamadai Sundar, Visalakshi Vaduganathan, Harikrishna Madadi Reddy