Patents by Inventor Deepak A. Mathaikutty

Deepak A. Mathaikutty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11010166
    Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Debabrata Mohapatra, Perry H. Wang, Xiang Zou, Sang Kyun Kim, Deepak A. Mathaikutty, Gautham N. Chinya
  • Patent number: 9785576
    Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Thiam Wah Loh, Per Hammarlund, Andreas Wasserbauer, Swee Chong Peter Kuan, Eckhard Delfs, Deepak A. Mathaikutty, Stephen J. Robinson, Gautham N. Chinya, Perry H. Wang, Chee Weng Tan, Hong Wang, Reza Fortas
  • Publication number: 20170286117
    Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Debabrata Mohapatra, Perry H. Wang, Xiang Zou, Sang Kyun Kim, Deepak A. Mathaikutty, Gautham N. Chinya
  • Patent number: 9003164
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Publication number: 20140208042
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Patent number: 8719547
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 6, 2014
    Assignee: Intel Corporation
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Publication number: 20110072234
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley