Patents by Inventor Deepak A. Ramappa
Deepak A. Ramappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160326636Abstract: Methods of affecting a material's properties through the implantation of ions, such as by using a plasma processing apparatus with a plasma sheath modifier. In this way, properties such as resistance to chemicals, adhesiveness, hydrophobicity, and hydrophilicity, may be affected. These methods can be applied to a variety of technologies. In some cases, ion implantation is used in the manufacture of printer heads to reduce clogging by increasing the materials hydrophobicity. In other embodiments, MEMS and NEMS devices are produced using ion implantation to change the properties of fluid channels and other structures. In addition, ion implantation can be used to affect a material's resistance to chemicals, such as acids.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Ludovic Godet, Christopher Hatem, Deepak Ramappa, Xianfeng Lu, Anthony Renau, Patrick Martin
-
Patent number: 9425027Abstract: Methods of affecting a material's properties through the implantation of ions, such as by using a plasma processing apparatus with a plasma sheath modifier. In this way, properties such as resistance to chemicals, adhesiveness, hydrophobicity, and hydrophilicity, may be affected. These methods can be applied to a variety of technologies. In some cases, ion implantation is used in the manufacture of printer heads to reduce clogging by increasing the materials hydrophobicity. In other embodiments, MEMS and NEMS devices are produced using ion implantation to change the properties of fluid channels and other structures. In addition, ion implantation can be used to affect a material's resistance to chemicals, such as acids.Type: GrantFiled: May 14, 2012Date of Patent: August 23, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Christopher Hatem, Deepak Ramappa, Xianfeng Lu, Anthony Renau, Patrick Martin
-
Patent number: 9330917Abstract: Methods of forming a passivation layer on a workpiece are disclosed. These methods utilize a SiC forming polymer to form the passivation layer. In addition, while the polymer is being heated to form SiC, a second result, such as annealing of the underlying workpiece, or firing of the metal contacts is achieved. For example, the workpiece may be implanted prior to coating it with the polymer. When the workpiece is heated, SiC is formed and the workpiece is annealed. In another embodiment, a workpiece is coating with the SiC forming polymer and metal pattern is applied to the polymer. The firing of workpiece causes the metal contacts to form and also forms SiC on the workpiece.Type: GrantFiled: February 20, 2013Date of Patent: May 3, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas Bateman, Deepak Ramappa
-
Patent number: 9293623Abstract: Techniques for manufacturing a device are disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for forming a solar cell. The method may comprise: implanting p-type dopants into a substrate via a blanket ion implantation process; implanting n-type dopants into the substrate via the blanket ion implantation process; and performing a first annealing process to form the p-type region and performing a second annealing process to form a second n-type region.Type: GrantFiled: October 26, 2012Date of Patent: March 22, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas P. T. Bateman, Deepak A. Ramappa
-
Patent number: 9062367Abstract: A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.Type: GrantFiled: September 10, 2012Date of Patent: June 23, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Ludovic Godet, Louis Steen, Deepak A. Ramappa
-
Patent number: 8937004Abstract: A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.Type: GrantFiled: April 19, 2013Date of Patent: January 20, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Anthony Renau, Ludovic Godet, Timothy J. Miller, Joseph C. Olson, Vikram Singh, James Buonodono, Deepak A. Ramappa, Russell J. Low, Atul Gupta, Kevin M. Daniels
-
Publication number: 20140273330Abstract: Methods of creating a workpiece having a smooth side and a textured side are disclosed. In some embodiments, a first side of a workpiece is doped, using ion implantation or diffusion, to create a doped layer. This doped layer of the first side may be more resistant to chemical treatment than the second side of the workpiece. This allows the second side of the workpiece to be textured without capping or otherwise protecting the doped first side, even though the doped layer of the first side physically contacts the chemical treatment. In some embodiments, a p-type dopant is used to create the doped layer. In some embodiments, the workpiece is processed to form a solar cell.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Vikram M. Bhosle, Christopher E. Dube, Deepak A. Ramappa
-
Patent number: 8815634Abstract: Dark currents within a photosensitive device are reduced through improved implantation of a species during its fabrication. Dark currents can be caused by defects in the photo-diode device, caused during the annealing, implanting or other processing steps used during fabrication. By amorphizing the workpiece in the photo-diode region, the number of defects can be reduced thereby reducing this cause of dark current. Dark current is also caused by stress induced by an adjacent STI, where the stress caused by the liner and fill material exacerbate defects in the workpiece. By amorphizing the sidewalls and bottom surface of the trench, defects created during the etching process can be reduced. This reduction in defects also decreases dark current in the photosensitive device.Type: GrantFiled: October 28, 2009Date of Patent: August 26, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak Ramappa, Dennis Rodier
-
Publication number: 20140202633Abstract: A system for processing a substrate includes a plasma chamber to produce a plasma including reactive gas ions at a first pressure, a bias supply to supply a bias between the plasma chamber and the substrate, a plasma sheath modifier disposed between the plasma chamber and substrate, the plasma sheath modifier having an aperture configured to direct the reactive ions toward the substrate in a beam having an ion beam profile, and a process chamber enclosing the substrate, the process chamber at a second pressure different than the first pressure to define a pressure differential.Type: ApplicationFiled: April 11, 2014Publication date: July 24, 2014Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
-
Patent number: 8778465Abstract: Methods of creating porous materials, such as silicon, are described. In some embodiments, plasma sheath modification is used to create ion beams of various incidence angles. These ion beams may, in some cases, form a focused ion beam. The wide range of incidence angles allows the material to be deposited amorphously. The porosity and pore size can be varied by changing various process parameters. In other embodiments, porous oxides can be created by adding oxygen to previously created layers of porous material.Type: GrantFiled: May 11, 2012Date of Patent: July 15, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Xiangfeng Lu, Deepak Ramappa
-
Publication number: 20140154834Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.Type: ApplicationFiled: May 9, 2013Publication date: June 5, 2014Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Nicholas P.T. Bateman, Atul Gupta, Christopher Hatem, Deepak Ramappa
-
Patent number: 8728951Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.Type: GrantFiled: July 31, 2012Date of Patent: May 20, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
-
Patent number: 8716155Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: GrantFiled: September 11, 2012Date of Patent: May 6, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak A. Ramappa, Kyu-Ha Shim
-
Publication number: 20140120647Abstract: Techniques for manufacturing a device are disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for forming a solar cell. The method may comprise: implanting p-type dopants into a substrate via a blanket ion implantation process; implanting n-type dopants into the substrate via the blanket ion implantation process; and performing a first annealing process to form the p-type region and performing a second annealing process to form a second n-type region.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Nicholas P.T. Bateman, Deepak A. Ramappa
-
Patent number: 8658513Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.Type: GrantFiled: May 2, 2011Date of Patent: February 25, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Fareen Adeni Khaja, Deepak Ramappa, San Yu, Chi-Chun Chen
-
Publication number: 20140038393Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
-
Patent number: 8614143Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.Type: GrantFiled: December 3, 2008Date of Patent: December 24, 2013Assignee: Texas Instruments IncorporatedInventors: Makarand R. Kulkarni, Deepak A. Ramappa
-
Patent number: 8603900Abstract: Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced.Type: GrantFiled: October 25, 2010Date of Patent: December 10, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Deepak Ramappa
-
Patent number: 8592230Abstract: A method of patterning a substrate includes providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate.Type: GrantFiled: April 21, 2011Date of Patent: November 26, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak A. Ramappa, Ludovic Godet
-
Patent number: 8586460Abstract: Methods of enabling the use of high wavelength lasers to create shallow melt junctions are disclosed. In some embodiments, the substrate may be preamorphized to change its absorption characteristics prior to the implantation of a dopant. In other embodiments, a single implant may serve to amorphize the substrate and provide dopant. Once the substrate is sufficiently amorphized, a laser melt anneal may be performed. Due to the changes in the absorption characteristics of the substrate, longer wavelength lasers may be used for the anneal, thereby reducing cost.Type: GrantFiled: September 21, 2011Date of Patent: November 19, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Deepak Ramappa