Patents by Inventor Deepak Agrawal
Deepak Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20260086144Abstract: Temperature-aware built-in self-test (BIST) control system for selectively controlling activation of BIST circuits in a processor-based system to maintain temperature limit and related methods. The temperature-aware BIST control system is configured to selectively control the number of BIST circuits in the processor-based system activated during the same time based on a temperature limit indicator related to a sensed temperature(s) in the processor-based system and whether such is within a defined temperature threshold(s) and/or temperature change rate threshold(s), which may be programmable. In this manner, the safety manager circuit can dynamically and selectively control the number of BIST circuits activated based on temperature according to the BIST control policy(ies) to reduce or avoid circuit failures due to excess temperature, while at the same time maximizing the staggering (i.e., overlapping) of BIST circuit activations to maximize testing speed.Type: ApplicationFiled: September 25, 2024Publication date: March 26, 2026Inventors: Dipti Ranjan Pal, Deepak Agrawal, Aseem Pandey, Shih-Hsin Jason Hu
-
Publication number: 20250277850Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.Type: ApplicationFiled: February 29, 2024Publication date: September 4, 2025Inventors: Arvind Jain, Vineet Ooramkumarath, Omid Chavoshi-Nejad, Deepak Agrawal, Madan Krishnappa
-
Publication number: 20250231745Abstract: Systems, and methods are described for a ML model generating sections of code based on inputs. The systems of generating code may receive inputs. The first input may be a description of problems for solving and a specification of an output. The second input may be variables. The third input may be data categories associated with the variables and the output. The fourth input may be responses to prompts. The prompts may be generated by a ML model based on association between the first, second, and third inputs. Boilerplate sections of code may be determined by the ML model. Missing portions of code are determined. Missing portions of code may be associated with core sections of code. The ML model may utilize the inputs to generate code to fill in missing portions of code. Generated code including missing portions and sections of generated code are provided to a user interface.Type: ApplicationFiled: December 23, 2024Publication date: July 17, 2025Inventors: William Moten, Hardik Punjabi, Zhiyu Liu, Nehal Sheth, Shreyas Shrivastava, Vasanth Chandrasekaran, Carissa Ann Melasippo, Nathalie Saade, Deepak Agrawal, Jordan David Kendall, Brian Walters
-
Publication number: 20250031689Abstract: Compositions and methods for cryopreservation including an amino acid at a concentration at, for example, between 50 mM and 1 M. Glutamate alone or combined with other amino acids and/or other cryoprotective molecules provides cell protection against freeze damage. Moreover, compositions and methods for cryopreservation may be provided with less or minimal toxicity by including one or more cryoprotectants at a concentration that is insufficient for crypopreservation of cells when used at that concentration alone.Type: ApplicationFiled: July 4, 2024Publication date: January 30, 2025Inventor: Deepak Agrawal
-
Patent number: 12032986Abstract: A time series forecasting system is disclosed that receives a forecast request identifying a forecast to be made for a future time point and a time series dataset to be used for making the requested forecast. The system selects a model to be used for making the requested forecast and determines a set of one or more attributes of the time series dataset. Based on the set of attributes, the system selects a compute instance either from a shared node pool or a dedicated instance having a shape to be used for training the selected model and generating a forecast. The system then generates a forecast result for the future time point using the trained model and provides the forecast result as a response to the forecast request.Type: GrantFiled: September 30, 2021Date of Patent: July 9, 2024Assignee: ORACLE INTERNATIONAL CORPORATIONInventor: Deepak Agrawal
-
Publication number: 20230101554Abstract: A time series forecasting system is disclosed that receives a forecast request identifying a forecast to be made for a future time point and a time series dataset to be used for making the requested forecast. The system selects a model to be used for making the requested forecast and determines a set of one or more attributes of the time series dataset. Based on the set of attributes, the system selects a compute instance either from a shared node pool or a dedicated instance having a shape to be used for training the selected model and generating a forecast. The system then generates a forecast result for the future time point using the trained model and provides the forecast result as a response to the forecast request.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Applicant: Oracle International CorporationInventor: Deepak Agrawal
-
Patent number: 11182542Abstract: A technique is described herein for effectively exposing annotation information in a document for use by various applications. The technique involves generating a tag tree data structure that identifies a collection of tag elements associated with a document. The technique also generates an overlay data structure that identifies a collection of annotations associated with the document. The overlay data structure also links the annotations to corresponding parts identified in the tag tree data structure. The technique then uses the tag tree data structure and the overlay data structure to provide information to a document-consuming component that conveys an order in which one or more annotations appear in the document relative to one or more parts in the document. According to one illustrative aspect, at least one annotation described by the overlay data structure is an active annotation, corresponding to a transient annotation that has not been saved.Type: GrantFiled: October 29, 2018Date of Patent: November 23, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Mahasweta Mitra, Mansi Awasthi, Deepak Agrawal, Mohit Bansal, Amit Kundlia, Shalu Gupta
-
Publication number: 20200134005Abstract: A technique is described herein for effectively exposing annotation information in a document for use by various applications. The technique involves generating a tag tree data structure that identifies a collection of tag elements associated with a document. The technique also generates an overlay data structure that identifies a collection of annotations associated with the document. The overlay data structure also links the annotations to corresponding parts identified in the tag tree data structure. The technique then uses the tag tree data structure and the overlay data structure to provide information to a document-consuming component that conveys an order in which one or more annotations appear in the document relative to one or more parts in the document. According to one illustrative aspect, at least one annotation described by the overlay data structure is an active annotation, corresponding to a transient annotation that has not been saved.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: Mahasweta MITRA, Mansi AWASTHI, Deepak AGRAWAL, Mohit BANSAL, Amit KUNDLIA, Shalu GUPTA
-
Patent number: 10630755Abstract: A problem with Internet access in a number of markets is the issue of data-limited network connections. Selective, on-demand consumption of web page data is provided. A user's browser presents a “light” version of a web page by loading compressed or low-fidelity versions of the web page images in place of the actual, higher-fidelity images. In the event that the user wishes to see the original higher-fidelity version of an image, clicking on the image or an associated icon loads the original-fidelity version of the image, replacing the low-fidelity version. The light version of the web page loads faster than would the original version of the web page, and requires less data to be downloaded when rendering the web page. This enables a user with a data-limited connection to select how he or she wishes to “spend” their data consumption.Type: GrantFiled: April 19, 2017Date of Patent: April 21, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Deepak Agrawal, Rahul Razdan, Bibhu Choudhary, Nithin Ismail, Saurabh Satnalika, Nithin Raj M
-
Publication number: 20180309817Abstract: A problem with Internet access in a number of markets is the issue of data-limited network connections. Selective, on-demand consumption of web page data is provided. A user's browser presents a “light” version of a web page by loading compressed or low-fidelity versions of the web page images in place of the actual, higher-fidelity images. In the event that the user wishes to see the original higher-fidelity version of an image, clicking on the image or an associated icon loads the original-fidelity version of the image, replacing the low-fidelity version. The light version of the web page loads faster than would the original version of the web page, and requires less data to be downloaded when rendering the web page. This enables a user with a data-limited connection to select how he or she wishes to “spend” their data consumption.Type: ApplicationFiled: April 19, 2017Publication date: October 25, 2018Inventors: Deepak AGRAWAL, Rahul RAZDAN, Bibhu CHOUDHARY, Nithin ISMAIL, Saurabh SATNALIKA, Nithin Raj M
-
Publication number: 20170024657Abstract: Systems and methods of generating geo-aware fuzzy autosuggestions for a search engine are disclosed. Transmissions received by a server system may be processed, the transmissions indicating characters received via a user interface as user input for a search query to a searching service. Information about a geographical location received by the server system may be processed, and a geographical area may be identified. A data store may be searched with an exact matching method to identify exact matches of the first set of characters with candidate data from the data store for geo-specific suggestions. Fuzzy searching operations may be performed based on the geographical area and the first set of characters. Geo-specific suggestions may be selected based on the fuzzy searching operations and may be transmitted to the end-user device to cause indication as a user-selectable option via the user interface to complete the search query.Type: ApplicationFiled: July 21, 2015Publication date: January 26, 2017Inventors: Sudheer Sahu, Guobin He, Vaibhav Chaudhary, Krishna Krishnamaneni, Deepak Agrawal
-
Publication number: 20160092829Abstract: A system is provided that manages consigned inventory. The system consumes consigned inventory items. The system further generates a consumption advice in response to the consumption of the consigned inventory items, where the consumption advice references a consignment agreement, a consignment order and a receipt. The system further communicates the consumption advice to a supplier. The consumption advice includes at least one of: a consumption advice number; a business unit; an inventory organization; a supplier; a supplier site; a start date; or an end date. The consumption advice includes one or more consumption advice lines, and each consumption advice line includes one or more consumption transactions.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Matthew Michael JONES, Manju Omprakash JUNEJA, Karthik GNANAMURTHY, Kalasagar KANDIKUPPA, Jason Yun Wei SHEU, William Edwin Rudge, V, Govinda Rao HADAGALI, Saket Sharan RAWAT, Vishal BERRY, Deepak AGRAWAL, Padmapriya PARTHASARATHY, PavanKumar Annapragada Naga VENKATA, Kathleen Mary GAHAN, Maneesh KUMAR, Susan Elizabeth FLIERL
-
Publication number: 20150323595Abstract: An apparatus for reducing test time is disclosed. The apparatus includes a processor operable to execute one or more modules to cause the processor to receive operational parameters associated with a first scan chain grouping circuitry and a second scan chain grouping circuitry of an integrated circuit design. The operational parameters include a number of initialization cycles of a first test signal selected for the first scan chain grouping circuitry, a number of initialization cycles of a second test signal selected for the second scan chain grouping circuitry, and a sum for a total number of cycles for the first test signal. The processor also determines a scan chain length for one of the first scan chain grouping circuitry or the second scan chain grouping circuitry based upon the operation parameters such that the total number of cycles of the first signal and the second signal are the same.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicant: LSI CorporationInventors: Ajaykumar B. Prajapati, Deepak Agrawal, Hariprasad U. Bhat
-
Publication number: 20150193564Abstract: An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock chain signal and to output an enable signal based upon the clock chain signal. The on-chip clock controller also includes a clock gating module that is communicatively coupled to the clock bits module. The clock gating module is configured to receive a clock signal and to selectively output either a signal corresponding to the clock signal or a non-transitioning signal based upon the enable signal for operating a state storage module.Type: ApplicationFiled: January 7, 2014Publication date: July 9, 2015Applicant: LSI CorporationInventors: Daryl Pereira, Deepak Agrawal, Sanjay T. Shinde, Sekar Manickam, Aanand Venkatachalam
-
Publication number: 20150160223Abstract: The invention provides a method for determining a prognosis of colorectal cancer in a colorectal cancer patient, comprising classifying said patient as having a good prognosis or a poor prognosis using measurements of a plurality of gene products in a cell sample taken from said patient, said gene products being respectively products of at least 1 of the genes listed in Table 1, or respective functional equivalents thereof, wherein said good prognosis predicts a positive response to standard chemotherapy regimens, and said poor prognosis predicts non-responsiveness. Provided herein, the invention includes a gene signature to predict which patients will to benefit from standard colon cancer therapy; alternatively, patients who are classified as non-responders may be more likely to benefit from a novel agent such as a Notch inhibitor.Type: ApplicationFiled: December 5, 2014Publication date: June 11, 2015Applicants: UNIVERSITY OF SOUTH FLORIDA, H.Lee Moffitt Cancer Center and Research Institute, Inc.Inventors: Timothy J. Yeatman, Deepak Agrawal, Adil Daud
-
Publication number: 20140365989Abstract: Methods and Systems to provide a production and delivery system, which acts as complete solution package, having in-built dynamic process flow designing, routing-rules, specification or data modeling capability, in-built specialized process libraries for the rapid building of execution platform and product libraries for supporting rapid processing and transformation of information products, providing a mechanism for rapid process flow designing, integrated management of information products processing and data transformation with accuracy.Type: ApplicationFiled: May 30, 2014Publication date: December 11, 2014Applicant: Innodata India Pvt. LtdInventors: Deepak AGRAWAL, Arun Kumar AGRAWAL
-
Patent number: 8832510Abstract: A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing.Type: GrantFiled: October 8, 2011Date of Patent: September 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Himanshu Kukreja, Deepak Agrawal
-
Patent number: 8504886Abstract: A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are identified. Each scan partition includes one or more scan chains of scan registers. One or more interacting registers connecting scan registers of a first scan partition and scan registers of a second scan partition are identified and combined to form an interacting scan chain. The embedded logic circuit is tested by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain.Type: GrantFiled: July 27, 2011Date of Patent: August 6, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Himanshu Kukreja, Deepak Agrawal
-
Patent number: 8495436Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.Type: GrantFiled: June 17, 2012Date of Patent: July 23, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Deepak Agrawal, Rachna Lalwani
-
Publication number: 20130117618Abstract: An integrated circuit includes a set of cells for operation in a functional mode and in a scan testing mode, and a spare cell. The cells are connected in a scan chain with scan data inputs connected to the outputs of preceding cells in the scan chain and respond to assertion of a scan enable signal. A clock gating element applies a functional clock signal to clock inputs of the cells in response to a gating enable signal in functional mode and a test clock signal in response to a test mode signal in scan testing mode. A functional data input of the spare cell latches the gating enable signal during the scan testing mode in response to de-assertion of the scan enable signal. The output of the spare cell is connected to the scan data input of one of the cells in response to the scan enable signal.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: HIMANSHU KUKREJA, DEEPAK AGRAWAL