Abstract: A computer-implemented system performs multi-level, user-initiated verification and selective credential sharing. A verification server issues secure API calls to multiple external providers to verify user-selected categories, including identity, employment, financial, education, criminal, court, family, social media, and medical. Provider data is normalized to a common schema, and fallback procedures are applied if primary verification fails. Verified results are stored in a user-controlled credential wallet. The wallet enables creation of share profiles specifying subsets of categories for disclosure in different contexts, each with configurable time limits, revocation rights, and access controls. Secure links or machine-readable codes provide recipient access to only the authorized categories. An immutable audit log records verification events, share profile creation, recipient access, and revocation, enabling compliance and evidentiary tracking while protecting personal data.

Abstract: A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.

Abstract: Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which points to the first hash map, and creating a second hash map at a second level which is immediately above the first level, where the second hash map maps at least one object to the first shared pointer.

Abstract: A clock relationship based re-convergence analysis method includes receiving, by a processing device, a register-transfer level (RTL) description of a design relating to an integrated circuit (IC). The method further includes identifying one or more clock domain crossing (CDC) synchronizers in the RTL description of the design, and generating a levelized topological abstract graph (LTAG) including a network of nodes. Each node includes a CDC synchronizer. The method further includes traversing the LTAG starting from a first output of the one or more CDC synchronizers, and responsive to determining that a first CDC synchronizer of the one or more CDC synchronizers is converging with a second CDC synchronizer, identifying a first potential convergence violation associated with the first CDC synchronizer and the second CDC synchronizer.

Abstract: Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which points to the first hash map, and creating a second hash map at a second level which is immediately above the first level, where the second hash map maps at least one object to the first shared pointer.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.

Abstract: Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.