Abstract: The disclosure relates generally to microphone and vibration sensor assemblies (100) having a transducer (102), like a microelectromechanical systems (MEMS) device, and an electrical circuit (103) disposed in a housing (110) configured for integration with a host device. The electrical circuit includes an output driver circuit, a low drop out (LDO) regulator circuit, and an over-voltage protection circuit with improved capacity and response time.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: The disclosure relates generally to microphone and vibration sensor assemblies (100) having a transducer (102), like a microelectromechanical systems (MEMS) device, and an electrical circuit (103) disposed in a housing (110) configured for integration with a host device. The electrical circuit includes an output driver circuit, a low drop out (LDO) regulator circuit, and an over-voltage protection circuit with improved capacity and response time.

Abstract: An apparatus includes a network interface and a processor. a network interface that receives a call report including an application programming interface (API) name of an API, a service name of a security service, and an identifier of a customer apparatus; and a processor configured to build a first first-order model, at least in part based on the API name, to perform a determination that an update for the security service is available, and to produce an update request, at least in part based on the first-order model and the determination, wherein the network interface transmits the update request to the customer apparatus.

Abstract: An apparatus includes a network interface that performs a reception of a launch request and receives a policy for a service. The launch request includes an identifier of a workload and an identifier of an application. A processor determines a customer security posture, at least in part based on the identifier of the workload and the identifier of the application. Further, the processor determines to deny the launch request, at least in part based on the policy and the customer security posture.

Abstract: An apparatus includes a network interface and a processor. The network interface receives an application programming interface (API) request, transmits a customer management request including an identifier of the customer apparatus, and receives a customer management response including a policy. The processor performs a security service on the API request, at least in part based on the policy.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Abstract: An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Abstract: This disclosure describes a system that facilitates analyzing a broad and continuously updated sample of recent written communications for the purpose of identifying emerging and important news and topic developments before they attract broad attention. The system continuously discovers topics and relationships between topics in the written communications as the communications are received. Individual topics and topic relationships are continuously analyzed for the purpose of detecting changes in the frequency and manner in which the topics are addressed and changes in the content that accompanies the topics. The system uses this analysis as the basis for identifying certain topics and the communications that address them as emerging, and therefore, important. The system uses a display feature to highlight these topics and communications for a user to review or investigate further.