Patents by Inventor Deepak C. Shetty
Deepak C. Shetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10114673Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.Type: GrantFiled: September 29, 2016Date of Patent: October 30, 2018Assignee: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Patent number: 9898301Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.Type: GrantFiled: June 20, 2014Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Patent number: 9817670Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.Type: GrantFiled: December 13, 2013Date of Patent: November 14, 2017Assignee: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Patent number: 9582323Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.Type: GrantFiled: June 19, 2014Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Publication number: 20170017525Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Patent number: 9535746Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.Type: GrantFiled: December 19, 2013Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Publication number: 20150178088Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Publication number: 20150178131Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.Type: ApplicationFiled: June 19, 2014Publication date: June 25, 2015Inventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Publication number: 20150169328Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.Type: ApplicationFiled: June 20, 2014Publication date: June 18, 2015Inventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Publication number: 20150169327Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Patent number: 7529864Abstract: A method and system for testing a remote I/O sub-assembly. The method including: allocating source memory, destination memory and DMA queue memory location in a memory of the remote I/O sub-assembly; writing a pattern of test data into the source memory location; writing a set of descriptors simulating data transfer commands into the DMA queue memory location; wrapping a first remote I/O port of the remote I/O sub-assembly to a second remote I/O port of the remote I/O sub-assembly with a remote I/O wrap cable; (e) configuring a DMA engine of the remote I/O sub-assembly to point to the DMA queue memory location and to the first and second remote I/O ports; and loading each descriptor of the set of descriptors into the DMA engine and transferring data from the source memory location to the destination memory location based on the descriptors.Type: GrantFiled: November 9, 2004Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Shakti Kapoor, Deepak C. Shetty