Patents by Inventor Deepak Chandra Pandey
Deepak Chandra Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11910597Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 2, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey
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Publication number: 20240006478Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.Type: ApplicationFiled: September 18, 2023Publication date: January 4, 2024Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
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Patent number: 11769795Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.Type: GrantFiled: October 12, 2021Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
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Publication number: 20230268419Abstract: A variety of applications can include apparatus having a transistor comprising a modified channel region to address sub-surface leakage issues of the transistor. A dielectric region can be structured to extend from a channel structure of the transistor downward into the substrate for the transistor, with the dielectric region disposed between the source of the transistor and the drain of the transistor to reduce leakage current paths between the source and the drain. The dielectric region can be structured with only dielectric material or with crystalline semiconductor material surrounded by dielectric material.Type: ApplicationFiled: July 27, 2022Publication date: August 24, 2023Inventors: Haitao Liu, Naveen Kaushik, Chittoor Ranganathan Parthasarathy, Deepak Chandra Pandey
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Patent number: 11569353Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.Type: GrantFiled: February 2, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Venkata Naveen Kumar Neelapala, Deepak Chandra Pandey
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Patent number: 11538809Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.Type: GrantFiled: August 31, 2020Date of Patent: December 27, 2022Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Deepak Chandra Pandey, Litao Yang, Srinivas Pulugurtha, Yunfei Gao, Haitao Liu
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Patent number: 11527620Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.Type: GrantFiled: May 11, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Deepak Chandra Pandey, Haitao Liu, Richard J. Hill, Guangyu Huang, Yunfei Gao, Ramanathan Gandhi, Scott E. Sills
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Patent number: 11515311Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.Type: GrantFiled: December 12, 2019Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Venkata Naveen Kumar Neelapala, Deepak Chandra Pandey, Naveen Kaushik
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Publication number: 20220301941Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.Type: ApplicationFiled: May 25, 2022Publication date: September 22, 2022Applicant: Micron Technology, Inc.Inventors: Deepak Chandra Pandey, Haitao Liu, Kamal M. Karda
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Patent number: 11430793Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: June 11, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Deepak Chandra Pandey, Venkata Naveen Kumar Neelapala, Haitao Liu
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Publication number: 20220262813Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Applicant: Micron Technology, Inc.Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey
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Publication number: 20220246727Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.Type: ApplicationFiled: February 2, 2021Publication date: August 4, 2022Inventors: Venkata Naveen Kumar Neelapala, Deepak Chandra Pandey
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Patent number: 11393928Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.Type: GrantFiled: August 24, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Haitao Liu, Yunfei Gao, Kamal M. Karda, Deepak Chandra Pandey, Sanh D. Tang, Litao Yang
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Patent number: 11373913Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.Type: GrantFiled: September 3, 2019Date of Patent: June 28, 2022Assignee: Micron Technology, Inc.Inventors: Deepak Chandra Pandey, Haitao Liu, Kamal M. Karda
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Patent number: 11348932Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: March 5, 2020Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey
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Publication number: 20220068929Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Kamal M. Karda, Deepak Chandra Pandey, Litao Yang, Srinivas Pulugurtha, Yunfei Gao, Haitao Liu
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Publication number: 20220045165Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.Type: ApplicationFiled: October 12, 2021Publication date: February 10, 2022Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
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Publication number: 20220036927Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 14, 2021Publication date: February 3, 2022Applicant: Micron Technology, Inc.Inventors: Naveen Kaushik, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey
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Publication number: 20210391337Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Inventors: Deepak Chandra Pandey, Venkata Naveen Kumar Neelapala, Haitao Liu
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Patent number: 11195560Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: December 10, 2019Date of Patent: December 7, 2021Assignee: Micron Technology, Inc.Inventors: Naveen Kaushik, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey