Abstract: A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.

Abstract: A power generation system includes an extraction device configured to extract moisture from an ambient air surrounding the system, a first tank configured to store the moisture, an electrolyzer configured to receive the moisture and produce hydrogen by performing a chemical process, a second tank configured to store the hydrogen produced by the electrolyzer, a generator system configured to generate electrical power from the hydrogen, and a controller configured to control operation of the extraction device and the electrolyzer.

Abstract: A power generation system includes an extraction device configured to extract moisture from an ambient air surrounding the system, a first tank configured to store the moisture, an electrolyzer configured to receive the moisture and produce hydrogen by performing a chemical process, a second tank configured to store the hydrogen produced by the electrolyzer, a generator system configured to generate electrical power from the hydrogen, and a controller configured to control operation of the extraction device and the electrolyzer.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: A power generation system includes an extraction device configured to extract moisture from an ambient air surrounding the system, a first tank configured to store the moisture, an electrolyzer configured to receive the moisture and produce hydrogen by performing a chemical process, a second tank configured to store the hydrogen produced by the electrolyzer, a generator system configured to generate electrical power from the hydrogen, and a controller configured to control operation of the extraction device and the electrolyzer.

Abstract: A multi-hybrid power generator and system that facilitate energy harvesting, generation, and storage from interchangeable power sources. The system including a plurality of battery banks; a plurality of power management devices, a plurality of battery banks; a first gearbox, a first generator, a second gearbox, a second generator, a crankshaft having a first crankshaft and a second crankshaft that allow for independent operation of one from the other, a multi-hybrid generator including a plurality of hydraulic electrical actuation devices (HEADs) for driving the first and second generators, and an intelligent power controller communicatively coupled to an electrical load and to the plurality of power management devices for selectively controlling power monitoring, power generation, power distribution and power storage between or to the plurality of battery banks, the at least one electrical load and the plurality of HEADs.

Abstract: A multi-hybrid power generator and system that facilitate energy harvesting, generation, and storage from interchangeable power sources. The system including a plurality of battery banks; a plurality of power management devices, a plurality of battery banks; a first gearbox, a first generator, a second gearbox, a second generator, a crankshaft having a first crankshaft and a second crankshaft that allow for independent operation of one from the other, a multi-hybrid generator including a plurality of hydraulic electrical actuation devices (HEADs) for driving the first and second generators, and an intelligent power controller communicatively coupled to an electrical load and to the plurality of power management devices for selectively controlling power monitoring, power generation, power distribution and power storage between or to the plurality of battery banks, the at least one electrical load and the plurality of HEADs.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: A method of treating headache disorders, by administering an effective amount of a composition of a psychedelic to the individual and treating the headache disorder. A method of treating migraine headache in an individual, by administering an effective amount of a psychedelic to the individual and reducing migraine headache burden. A method of treating cluster headache in an individual, by administering an effective amount of a psychedelic to the individual and reducing cluster headache burden. A method of treating headache disorders, by administering a single treatment of a psychedelic to an individual and providing a long term effect in preventing headaches.

Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.

Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.

Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.