Abstract: A method for calibrating an optical transceiver. The method can include configuring optical switches to enable routing at least one output signal of modulator circuitry operably coupled to a first receive path of a coherent optical transceiver. The method can include configuring the input to at least one modulator to generate at least one first stimulus signal. The method can include configuring a path from the first receiver analog-to-digital converter to an adaptive algorithm circuitry. The method can include adapting at least one bias setting of a photodiode associated with the first receiver in response to at least one first stimulus detected at the first receiver analog-to-digital converter to an adaptive algorithm circuitry. The method can include determining an optimum value of a photodiode associated with the first receiver.

Abstract: A clock data recovery (CDR) apparatus can include an interpolator circuitry to interpolate an input received signal and to generate an output signal removing the sampling clock offsets. The apparatus can include timing error detector (TED) circuitry coupled to process the output signal and to provide a timing error as feedback to the interpolator circuitry, the timing error being adjusted by gain factors used in at least one of an automatic gain control (AGC) circuitry and an orthogonalization circuitry. The apparatus can include loop filter (LF) circuitry to filter the timing error to remove noise effects. The apparatus can include numerically controlled oscillator (NCO) circuitry to adjust for a basepoint and fractional interval used to adjust resampling coefficients within the interpolator circuitry.

Abstract: An apparatus can include transceiver circuitry to receive an input signal from a target apparatus. The apparatus can further include a processing circuitry to determine position information of a source object and a target object. Based on the position information, the processing circuitry can calculate a relative velocity and determine a Doppler shift or carrier frequency offset in the input signal based on the relative velocity. The processing circuitry can adjust a local oscillator frequency based on a Doppler measured using the position information in an initial link acquisition phase. The processing circuitry can track the Doppler continuously over a range of tens of gigahertz accounting for Doppler phase ambiguities, and correct for a tracked Doppler shift by partially adjusting a local oscillator frequency and by correcting a residual Doppler shift digitally.

Abstract: A method for authenticating features reported by a vehicle includes receiving, from a network, a map of an area with confidence weights corresponding to each feature on the map and/or a list of trusted users; upon the vehicle entering the area, checking whether the vehicle is on the list of trusted users; and checking features reported from the vehicle and matching the features to the map of the area.

Abstract: A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.

Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.

Abstract: An apparatus can include at least two circuit portions having separate power sequencer circuitry. The apparatus can further include processing circuitry configured to control at least one portion of the at least two circuit portions to operate at an initial low power level and subsequent higher power levels to full operation.

Abstract: A converter can include a number of time-to-voltage converters (TVCs) each receiving an input time-domain signal. The input time-domain signal can represent a different sample than input time-domain signals of the other TVCs. The converter can also include a capacitive element coupled to outputs of the TVCs to receive a combined output signal of the TVCs. The capacitive element can provide an input capacitance of an analog-to-digital converter (ADC). Other methods and apparatuses are described.

Abstract: Systems, apparatuses and methods include technology that executes, with a compute-in-memory (CiM) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (CnM) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (CoM) element, third computations based on third data associated with the workload. The technology further receives, with a multiplexer, processed data from a first element of the CiM element, the CnM element and the CoM element, and provides, with the multiplexer, the processed data to a second element of the CiM element, the CnM element and the CoM element.

Abstract: A communication device for a vehicle to communicate features about the vehicle's environment includes one or more processors configured to receive a communication from another device, wherein the communication includes a global reference coordinate system for an area covered by the other device and a number of allowed transmissions to be sent from the vehicle; transform stored data about the vehicle's environment based on the global reference coordinate system; divide the transformed stored data into a plurality of subsets of data; and select one or more subsets of data from the plurality of subsets for transmission according to the number of allowed transmissions.

Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

Abstract: A processor may include an interface configured to receive input data and instructions, and to provide processed data, a shared memory configured to store the received input data, an instruction memory configured to store the received instructions, a plurality of processing elements configured to perform a first set of arithmetic operations. The processor may further include a controller configured to control the plurality of processing elements and one or more accelerators based on the received instructions to obtain the processed data, by which the plurality of processing elements performs the first set of arithmetic operations and the one or more accelerators perform a second set of arithmetic operations based on the received input data stored in the shared memory.

Abstract: A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

Abstract: According to various embodiments, a method for operating a vehicle may include determining a vehicular area having traffic conditions or characteristics different from traffic conditions of a current or previous location of the vehicle; obtaining traffic and driving information for the determined vehicular region; changing or updating one or more of driving model parameters of a safety driving model during operation of the vehicle based on the obtained traffic and driving information; and controlling the vehicle to operate in accordance with the safety driving model using the one or more changed or updated driving model parameters. A vehicle may seamlessly update operational rules and/or handover of traffic and driving information for transitioning from one region to another.

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

Abstract: Technology for generating an SRAM-based in-memory computing macro includes replacing a SRAM cell cluster defined by a generic SRAM macro with a single-bit multi-bank cluster, the single-bit multi-bank cluster including a plurality of CiM SRAM cells and a plurality of C-2C capacitor ladder cells, arranging a plurality of single-bit multi-bank clusters to form a multi-bit multi-bank cluster, and arranging a plurality of multi-bit multi-bank clusters into a multi-dimensional MAC computational unit within a region of the generic SRAM macro, where an output of at least two of the multi-bit multi-bank clusters are electrically coupled to form an output analog activation line, and where a plurality of bit lines and a plurality of word lines remain at the same grid locations as provided in the generic SRAM macro. Embodiments include arranging a plurality of multi-dimensional MAC computational units into an in-memory MAC computing array.

Abstract: Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.