Abstract: A decoder device can include an input to provide a stream of data elements to a data decoding pipeline. The device can further include an early termination element coupled at a coupling point of one or more of the input or at a pipeline stage of the data decoding pipeline. The early termination element can remove a data element from the stream at the respective coupling point based on a determination that the data element is to be removed from the stream. The early termination element can further provide the removed data element to output circuitry of the decoder device. Other methods and apparatuses are described.

Abstract: A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

Abstract: Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

Abstract: Techniques and mechanisms providing a mode of random number generation to satisfy a requirement for a consumer of random numbers. In an embodiment, a device comprises a Gaussian random number generator (GRNG) circuit, multiple uniform random number generator URNG circuits, and circuitry which is coupled between the GRNG circuit and the URNG circuits. Based on an indication of one or more required performance characteristics and/or one or more required statistical characteristics, a controller identifies a corresponding one of multiple available random number generation (RNG) modes. The controller communicates control signals to provide the mode with the circuitry. In another embodiment, the control signals configure the circuitry to select one or more of the URNG circuits for use in calculating random numbers with the GRNG circuit.

Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

Abstract: Bayesian Inference based communication receiver employs Markov-Chain Monte-Carlo (MCMC) sampling for performing several of the main receiver functionalities. The channel estimator estimates the multipath channel coefficients corresponding to a signal received with fading. The symbol demodulator demodulates the received signal according to a QAM constellation, so as to generate a demodulated signal, and estimate the transmitted symbols. The decoder reliably decodes the demodulated signals to generate an output bit sequence, factoring in redundancy induced at a certain code rate. A universal sampler may be configured to use MCMC sampling for generating estimates of channel coefficients, transmitted symbols or decoder bits, for aforementioned functionalities, respectively. The samples may then be used in one or more of the receiver tasks: channel estimation, signal demodulation, and decoding, which leads to a more scalable, reusable, power/area efficient receiver.

Abstract: An apparatus can include transceiver circuitry to receive an input signal from a target apparatus. The apparatus can further include a processing circuitry to determine position information of a source object and a target object. Based on the position information, the processing circuitry can calculate a relative velocity and determine a Doppler shift or carrier frequency offset in the input signal based on the relative velocity. The processing circuitry can adjust a local oscillator frequency based on a Doppler measured using the position information in an initial link acquisition phase. The processing circuitry can track the Doppler continuously over a range of tens of gigahertz accounting for Doppler phase ambiguities, and correct for a tracked Doppler shift by partially adjusting a local oscillator frequency and by correcting a residual Doppler shift digitally.

Abstract: A clock data recovery (CDR) apparatus can include an interpolator circuitry to interpolate an input received signal and to generate an output signal removing the sampling clock offsets. The apparatus can include timing error detector (TED) circuitry coupled to process the output signal and to provide a timing error as feedback to the interpolator circuitry, the timing error being adjusted by gain factors used in at least one of an automatic gain control (AGC) circuitry and an orthogonalization circuitry. The apparatus can include loop filter (LF) circuitry to filter the timing error to remove noise effects. The apparatus can include numerically controlled oscillator (NCO) circuitry to adjust for a basepoint and fractional interval used to adjust resampling coefficients within the interpolator circuitry.

Abstract: A method for calibrating an optical transceiver. The method can include configuring optical switches to enable routing at least one output signal of modulator circuitry operably coupled to a first receive path of a coherent optical transceiver. The method can include configuring the input to at least one modulator to generate at least one first stimulus signal. The method can include configuring a path from the first receiver analog-to-digital converter to an adaptive algorithm circuitry. The method can include adapting at least one bias setting of a photodiode associated with the first receiver in response to at least one first stimulus detected at the first receiver analog-to-digital converter to an adaptive algorithm circuitry. The method can include determining an optimum value of a photodiode associated with the first receiver.

Abstract: An apparatus can include transceiver circuitry to receive an input signal from a target apparatus. The apparatus can further include a processing circuitry to determine position information of a source object and a target object. Based on the position information, the processing circuitry can calculate a relative velocity and determine a Doppler shift or carrier frequency offset in the input signal based on the relative velocity. The processing circuitry can adjust a local oscillator frequency based on a Doppler measured using the position information in an initial link acquisition phase. The processing circuitry can track the Doppler continuously over a range of tens of gigahertz accounting for Doppler phase ambiguities, and correct for a tracked Doppler shift by partially adjusting a local oscillator frequency and by correcting a residual Doppler shift digitally.

Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.

Abstract: An apparatus can include at least two circuit portions having separate power sequencer circuitry. The apparatus can further include processing circuitry configured to control at least one portion of the at least two circuit portions to operate at an initial low power level and subsequent higher power levels to full operation.

Abstract: A converter can include a number of time-to-voltage converters (TVCs) each receiving an input time-domain signal. The input time-domain signal can represent a different sample than input time-domain signals of the other TVCs. The converter can also include a capacitive element coupled to outputs of the TVCs to receive a combined output signal of the TVCs. The capacitive element can provide an input capacitance of an analog-to-digital converter (ADC). Other methods and apparatuses are described.

Abstract: Systems, apparatuses and methods include technology that executes, with a compute-in-memory (CiM) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (CnM) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (CoM) element, third computations based on third data associated with the workload. The technology further receives, with a multiplexer, processed data from a first element of the CiM element, the CnM element and the CoM element, and provides, with the multiplexer, the processed data to a second element of the CiM element, the CnM element and the CoM element.

Abstract: A communication device for a vehicle to communicate features about the vehicle's environment includes one or more processors configured to receive a communication from another device, wherein the communication includes a global reference coordinate system for an area covered by the other device and a number of allowed transmissions to be sent from the vehicle; transform stored data about the vehicle's environment based on the global reference coordinate system; divide the transformed stored data into a plurality of subsets of data; and select one or more subsets of data from the plurality of subsets for transmission according to the number of allowed transmissions.

Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.