Abstract: A content addressable memory system for accessing blocks of data stored in circular charge coupled shift registers in response to a tag word presented to a directory unit comprising circular charge coupled shift registers. The memory includes clocking and logic circuitry for providing selective, high speed clocking of blocks and directory unit registers for both read and write operations. Additional logic facilitates masked directory searches at selective clock rates. Automatic synchronization of fast and slow clocked registers is provided by a counter of predetermined count corresponding to the formula N/(1-H) where H is the number of bits per circular register and H equals the ratio of slow to fast shift rates. A use bit register in the directory unit and a bookkeeping loop register in each module further aid in synchronization of the memory operation.

Abstract: A stack memory having a last-in-first-out memory organization comprising a plurality of pairs of two-phase charge coupled device shift registers arranged into a plurality of rows, the CCD registers of each pair being interconnected by digital logic to provide a circular shift register cell and to direct data into and out of the cell. Each cell is interconnected through its logic to an adjacent cell within the same row, and each row of a plurality of circular shift register cells is interconnected between an input buffer register and an output buffer register. The input buffer register is used to write data into each one of the plurality of rows of cells, and the output buffer register is used to retrieve the data from each row of cells.