Patents by Inventor Deepak K. Gupta

Deepak K. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9946566
    Abstract: A processor comprises a register to store a first pointer to a context data structure specifying a virtual machine context, the context data structure comprising a first field to store a second pointer to a plurality of realm switch control structures (RSCSs), and an execution unit comprising a logic circuit to execute a virtual machine (VM) according to the virtual machine context, wherein the VM comprises a guest operating system (OS) comprising a plurality of kernel components, and wherein each RSCS of the plurality of RSCSs specifies a respective component context associated with a respective kernel component of the plurality of kernel components, and execute a first kernel component of the plurality of kernel components using a first component context specified by a first RSCS of the plurality of RSCSs.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Deepak K. Gupta, Ravi L. Sahita, Barry E. Huntley
  • Patent number: 9785800
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state; responsive to executing a control transfer instruction having a pre-defined subcode, remain in the first execution state; responsive to executing a control transfer instruction not having the pre-defined subcode, transition into a second execution state; and responsive to determining, in the second execution state, that a next instruction to be executed differs from an ENDBRANCH instruction, raise an execution exception.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Ravi L. Sahita, Deepak K. Gupta
  • Publication number: 20170249261
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Application
    Filed: June 7, 2016
    Publication date: August 31, 2017
    Applicant: Intel Corporation
    Inventors: DAVID M. DURHAM, RAVI L. SAHITA, GILBERT NEIGER, VEDVYAS SHANBHOGUE, ANDREW V. ANDERSON, MICHAEL LEMAY, JOSEPH F. CIHULA, ARUMUGAM THIYAGARAJAH, ASIT K. MALLICK, BARRY E. HUNTLEY, DAVID A. KOUFATY, DEEPAK K. GUPTA, BAIJU V. PATEL
  • Publication number: 20170249260
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Application
    Filed: April 1, 2016
    Publication date: August 31, 2017
    Inventors: RAVI L. SAHITA, GILBERT NEIGER, VEDVYAS SHANBHOGUE, DAVID M. DURHAM, ANDREW V. ANDERSON, DAVID A. KOUFATY, ASIT K. MALLICK, ARUMUGAM THIYAGARAJAH, BARRY E. HUNTLEY, DEEPAK K. GUPTA, MICHAEL LEMAY, JOSEPH F. CIHULA, BAIJU V. PATEL
  • Publication number: 20170228535
    Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.
    Type: Application
    Filed: February 4, 2016
    Publication date: August 10, 2017
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak K. Gupta
  • Publication number: 20170220466
    Abstract: Embodiments of an invention for sharing a guest physical address space between virtualized contexts are disclosed. In an embodiment, a processor includes a cache memory and a memory management unit. The cache memory includes a plurality of entry locations, each entry location having a guest physical address field and a host physical address field. The memory management unit includes page-walk hardware and cache memory access hardware. The page-walk hardware is to translate a guest physical address to a host physical address using a plurality of page table entries. The cache memory access hardware is to store the guest physical address and the host physical address in the cache memory only if a shareability indicator in at least one of the page table entries is set.
    Type: Application
    Filed: January 30, 2016
    Publication date: August 3, 2017
    Inventors: Deepak K. Gupta, Baiju V. Patel, Andrew V. Anderson, Gilbert Neiger, Ravi L. Sahita
  • Publication number: 20170185803
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state; responsive to executing a control transfer instruction having a pre-defined subcode, remain in the first execution state; responsive to executing a control transfer instruction not having the pre-defined subcode, transition into a second execution state; and responsive to determining, in the second execution state, that a next instruction to be executed differs from an ENDBRANCH instruction, raise an execution exception.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Vedvyas Shanbhogue, Ravi L. Sahita, Deepak K. Gupta
  • Publication number: 20170177339
    Abstract: Methods and apparatuses relating to switching of a shadow stack pointer are described. In one embodiment, a hardware processor includes a hardware decode unit to decode an instruction, and a hardware execution unit to execute the instruction to: pop a token for a thread from a shadow stack, wherein the token includes a shadow stack pointer for the thread with at least one least significant bit (LSB) of the shadow stack pointer overwritten with a bit value of an operating mode of the hardware processor for the thread, remove the bit value in the at least one LSB from the token to generate the shadow stack pointer, and set a current shadow stack pointer to the shadow stack pointer from the token when the operating mode from the token matches a current operating mode of the hardware processor.
    Type: Application
    Filed: December 20, 2015
    Publication date: June 22, 2017
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak K. Gupta
  • Publication number: 20170090966
    Abstract: A processor comprises a register to store a first pointer to a context data structure specifying a virtual machine context, the context data structure comprising a first field to store a second pointer to a plurality of realm switch control structures (RSCSs), and an execution unit comprising a logic circuit to execute a virtual machine (VM) according to the virtual machine context, wherein the VM comprises a guest operating system (OS) comprising a plurality of kernel components, and wherein each RSCS of the plurality of RSCSs specifies a respective component context associated with a respective kernel component of the plurality of kernel components, and execute a first kernel component of the plurality of kernel components using a first component context specified by a first RSCS of the plurality of RSCSs.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventors: DEEPAK K. GUPTA, RAVI L. SAHITA, BARRY E. HUNTLEY
  • Patent number: 7902073
    Abstract: A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: March 8, 2011
    Assignee: Lam Research Corporation
    Inventors: Ji Soo Kim, Sangheon Lee, Deepak K. Gupta, S. M. Reza Sadjadi
  • Publication number: 20080146032
    Abstract: A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 19, 2008
    Inventors: Ji Soo Kim, Sangheon Lee, Deepak K. Gupta, S. M. Reza Sadjadi