Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.

Abstract: The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect area grid array chip scale packages (“CSPs”) to printed wiring boards (“PWBs”). The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the corresponding connecting surfaces of the area grid array CSP. Next, the securing tie bars and the tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB.

Abstract: A method and system of utilizing inexpensively manufactured, electrically conductive and mechanically compliant disks to interconnect an area grid array (“AGA”) chip to a printed wiring board. The conductive disk shaped leads are stamped from a thin sheet of conductive material. To increase solderability and protect the disk surface, the disks can be plated with tin or an equivalent material. Each disk is positioned tangent to the surface of an AGA chip in a specific orientation. One edge of each disk is electrically connected and mechanically secured to a corresponding conductive pad located on the surface of the AGA chip. The opposite edge of each conductive disk is positioned to align with a corresponding conductive surface pad on a printed wiring board (“PWB”). Each opposite edge is electrically connected and mechanically secured to the surface of the PWB, thereby establishing a compliant electrical connection between the AGA chip and the PWB.

Abstract: A multilayer package includes a plurality of interconnected large-layer-count (LLC) substrates. The LLC substrates each include conductive pads on the top and bottom surfaces of the substrate, a via in the substrate including conductive material to contact the pads on the top and bottom surfaces, and a post on a pad over the via. The posts of the substrates confront and abut each other, and are electrically bonded together. A non-flowable adhesive film mechanically bonds the LLC substrates, and has an aperture receiving the posts of the substrates.

Abstract: A method and apparatus for performing a function on an integrated circuit having a plurality of electrical contact pads is disclosed. The apparatus includes a substrate for performing the function on the integrated circuit, the substrate having a plurality of electrical contact pads and at least one electrical test contact pad. A centering housing encompasses the integrated circuit and centers the integrated circuit with respect to the substrate such that the plurality of electrical contact pads of the integrated circuit electrically connects with the plurality of electrical contact pads of the substrate. A test connector connects integrated circuit to the substrate.

Abstract: A method and apparatus for performing a function on an integrated circuit having a plurality of electrical contact pads is disclosed. The apparatus includes a substrate for performing the function on the integrated circuit, the substrate having a plurality of electrical contact pads and at least one electrical test contact pad. A centering housing encompasses the integrated circuit and centers the integrated circuit with respect to the substrate such that the plurality of electrical contact pads of the integrated circuit electrically connects with the plurality of electrical contact pads of the substrate. A test connector connects integrated circuit to the substrate.

Abstract: A process of laminating a large-layer-count (LLC) substrates includes formation of first and second vias through respective substrates. A conductive path is formed through each of the respective vias, and posts are formed on the respective vias, electrically connected to the respective conductive path. A non-flowable adhesive layer having an aperture is provided between the LLC substrates so that the posts confront each other through the aperture. The LLC substrates are pressed together through the non-flowable adhesive layer to mechanically bond them together, and so that the posts abut each other. Simultaneously, the posts are electrically bonded to each other in the aperture.

Abstract: A process of measuring coplanarity of an array of conductive elements on a circuit device is disclosed. Light is impinged from a reference plane onto an element of the array at a predetermined angle of incidence. Light is also impinged from the reference plane onto a reflective feature on a measurement plane determined by three points of the circuit device having highest elevations from a base of the circuit device, at the same predetermined angle of incidence. A response of the light impinged onto the element of the array and the reflective feature on the measurement plane is measured to determine coplanarity of the array.

Abstract: A method of combining a metal component and a base metal of an article to form a pattern of the article. The method comprises applying the metal component to a carrier, the metal component shaped like the pattern; placing the metal component against the base metal; and supplying heat such that the base metal and the metal component alloy.

Abstract: An alignment mark system and method of using the same wherein each mask of a sequence of masks includes a mask sequence indicium, a first alignment feature and a second alignment feature spaced from the first alignment feature. Each of the mask sequence indicium, the first alignment feature and the second alignment feature produce a corresponding structure as a result of the photolithographic process. The structure resulting from the second alignment feature is aligned with the first alignment feature of the immediately succeeding mask for proper alignment of the mask sequence.

Abstract: The present invention is an integrated heat sink module and a method of fabricating conductive structures on a substrate. The method of the present invention includes cleaning a substrate material to remove any impurities present on the substrate surface. The method further includes placing a protective layer resilient to chemicals used in conductive structure formation, on a first surface. The first surface is opposite a second surface on which conductive structures are formed. The method includes forming conductive structures on the second surface of the substrate. The protective layer is then removed from the first surface of the substrate.

Abstract: A curved lead provides a mechanical and electrical connection between a board contact on a circuit board and a chip contact associated with a circuit chip. The chip can be mounted to the circuit board, to a chip carrier or to a multiple-chip module. The curved lead is substantially entirely plated with solder and is formed of a single piece of conductive material. The curved lead has a first surface for connection to the chip contact and a second surface, generally parallel to the first surface, for connection to the board contact. The first and second surfaces are connected by at least one curved portion and are arranged to mount the circuit chip to the circuit board with the solder in a compliant, generally parallel arrangement substantially free of stress.

Abstract: An apparatus and method for a cleaning process control is disclosed. The apparatus includes two parallel plates of glass that have a plurality of shims positioned therebetween and a means for clamping these plates of glass firmly against the shims. A contaminant is positioned between the plates of glass and the apparatus is cleaned using a selected cleaning process. The apparatus can then be inspected to determine the effectiveness of a particular cleaning process by peering through the transparent glass plates to inspect for any remaining contaminant. The apparatus can then be cleaned more extensively and used again to check a different cleaning process.

Abstract: A curved lead provides a mechanical and electrical connection between a board contact on a circuit board and a chip contact associated with a circuit chip. The chip can be mounted to the circuit board, to a chip carrier or to a multiple-chip module. The curved lead is substantially entirely plated with solder and is formed of a single piece of conductive material. The curved lead has a first surf ace for connection to the chip contact and a second surface, generally parallel to the first surface, for connection to the board contact. The first and second surfaces are connected by at least one curved portion and are arranged to mount the circuit chip to the circuit board with the solder in a compliant, generally parallel arrangement substantially free of stress.

Abstract: A circuit module includes a multilayer circuit board having a plurality of alternate layers defining circuit paths and insulation with conductive vias between selected circuit paths of different layers. A hermetic seal is sealed to the top layer of the multilayer circuit board, and the circuit paths and/or vias are selectively connected to external pads by vias extending through the multilayer circuit board, one via terminating at a pad internal to the sealed region and another via terminating at the external pad. In one form, the vias providing the external connection extend into a substrate supporting the board, and circuit paths in the substrate electrically connect the vias together. In a second form, the vias providing the external connection are electrically connected together by selected circuit paths in the circuit board. A conductive anchor extends through the circuit board to the substrate to provide an anchor for the seal.

Abstract: An apparatus and method for a cleaning process control is disclosed. The apparatus includes a printed wire circuit board that is made on a Pyrex glass or other transparent substrate. Components are attached to the printed wire circuit board and then the circuit card assembly which is formed is cleaned using a selected cleaning process. The circuit card assembly can then be inspected to determine the effectiveness of a particular cleaning process by flipping over the transparent circuit card, peering through the substrate to inspect for corrosion and solder balls. The circuit card assembly can then be cleaned more extensively and used again to check a different cleaning process.

Abstract: A compliant S-shaped lead for resiliently supporting an integrated circuit chip package in spaced relation generally parallel to a printed circuit board. The S-lead bends and twists to absorb forces which would otherwise be exerted on solder joints due to temperature cycling and vibration. The symmetrical S-lead self-centers on both the package and PC board to provide minimum stress. The leads are held by a support strip for connection to the chip carrier. Thereafter, the support strip is removed and the carrier positions the leads for connection to the circuit board.