Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

Abstract: A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

Abstract: An approach is disclosed that that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruc

Abstract: Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.

Abstract: An approach is disclosed that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruction

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

Abstract: Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.

Abstract: A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

Abstract: Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

Abstract: Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.

Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

Abstract: Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n?1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Abstract: Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n?1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Abstract: An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.

Abstract: A 3× circuit for partial product generation used in a radix-8 multiplier receiving only a single multiplicand input. Rather than providing 2-inputs to the adder (a 2× of multiplicand and the multiplicand itself), the new 3× circuit uses the multiplicand as the only input. Thus, in terms of connections at the multiplier circuit level, only one bus is required to connect to the input of the new 3× circuit. The 3× generation adder circuit further operates at a reduced number of logic levels and speeds up the critical path by taking advantage of the repetition and fixed spatial separation of the bits for the adder inputs.

Abstract: An approach for determining a value representing the number of leading zero count value in a binary input data word, is described. The binary input data word contains random data. The binary input data word is logically divided into odd and even bit positions. The approach includes a first comparator circuit for comparing data in the odd bit positions to data in the even bit positions. The approach further includes a second comparator circuit for comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The approach further includes a half-width leading zero counting circuit that provides a value representing the number of leading zero bits in the binary input data word.

Abstract: A 3× circuit for partial product generation used in a radix-8 multiplier receiving only a single multiplicand input. Rather than providing 2-inputs to the adder (a 2× of multiplicand and the multiplicand itself), the new 3× circuit uses the multiplicand as the only input. Thus, in terms of connections at the multiplier circuit level, only one bus is required to connect to the input of the new 3× circuit. The 3× generation adder circuit further operates at a reduced number of logic levels and speeds up the critical path by taking advantage of the repetition and fixed spatial separation of the bits for the adder inputs.