Abstract: A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.

Abstract: In accordance with an embodiment of the present invention, a memory cell includes a two terminal access device disposed above a semiconductor substrate. The access device includes a two terminal resistive switching device having substantially zero retention. The two terminal resistive switching device has a low resistance state and a high resistance state. A memory device is disposed above the semiconductor substrate. The memory device is coupled to the access device.

Abstract: A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.

Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.

Abstract: A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.

Abstract: Structures and methods for recovering data in a semiconductor memory device are disclosed herein. In one embodiment, a method of recovering data in a semiconductor memory device, can include: (i) pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell; (ii) storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state; (iii) mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and (iv) performing a recovery of the first data state by reducing the resistance of the first memory cell.

Abstract: A method of operating a resistive switching device includes applying a program stress to a two terminal resistive memory unit. The program stress is applied at a program voltage configured to change a state of the memory unit from a first state to a second state. The method further includes applying a verification/stabilization stress to the two terminal resistive memory unit. The verification/stabilization stress is applied at a verification/stabilization voltage. An erase stress is applied to the two terminal resistive memory unit. The erase stress is applied at an erase voltage configured to change a state of the memory unit from the second state to the first state. The verification/stabilization voltage is between the program voltage and the erase voltage.

Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming the programmable impedance element can include: (i) receiving a program command to be executed on the programmable impedance element; (ii) performing a program operation on the programmable impedance element in response to the program command; (iii) determining if the program operation successfully programmed the programmable impedance element; and (iv) performing an erase operation for programming the programmable impedance element in response to the program operation failing to successfully program the programmable impedance element.

Abstract: A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.

Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.