Patents by Inventor Deepak Kodihalli
Deepak Kodihalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768727Abstract: Described are techniques including a computer-implemented method of determining, by a service processor, that a first set of callouts of a first error log matches a previous set of callouts of a previous error log. The method further comprises combining the first error log with the previous error log in a first group in a service processor log of the service processor. The method further comprises transmitting information related to the first group to a management console communicatively coupled to the service processor.Type: GrantFiled: November 23, 2021Date of Patent: September 26, 2023Assignee: International Business Machines CorporationInventors: Sampa Misra, Deepak Kodihalli, Giridhari Krishnan
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Patent number: 10623383Abstract: Disclosed aspects relate to symmetric multiprocessing (SMP) management. A first SMP topology may be identified by a service processor firmware. The first SMP topology may indicate a first set of connection paths for a plurality of processor chips of a multi-node server. A second SMP topology may be identified by the service processor firmware. The second SMP topology may indicate a second set of connection paths for the plurality of processor chips of the multi-node server. The second SMP topology may differ from the first SMP topology. An error event related to the first SMP topology may be detected. A set of traffic may be routed using the second SMP topology. The set of traffic may be routed by the service processor firmware in response to detecting the error event related to the first SMP topology.Type: GrantFiled: June 27, 2018Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Deepak Kodihalli, Venkatesh Sainath, Dhruvaraj Subhashchandran
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Patent number: 10540244Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology in response to determining that the first processor is directed connected to an oscillator. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure, the system re-configures to the second TOD topology.Type: GrantFiled: October 31, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Manish Kumar Chowdhary, Deepak Kodihalli
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Patent number: 10375038Abstract: Disclosed aspects relate to symmetric multiprocessing (SMP) management. A first SMP topology may be identified by a service processor firmware. The first SMP topology may indicate a first set of connection paths for a plurality of processor chips of a multi-node server. A second SMP topology may be identified by the service processor firmware. The second SMP topology may indicate a second set of connection paths for the plurality of processor chips of the multi-node server. The second SMP topology may differ from the first SMP topology. An error event related to the first SMP topology may be detected. A set of traffic may be routed using the second SMP topology. The set of traffic may be routed by the service processor firmware in response to detecting the error event related to the first SMP topology.Type: GrantFiled: November 30, 2016Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Deepak Kodihalli, Venkatesh Sainath, Dhruvaraj Subhashchandran
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Patent number: 10282243Abstract: Embodiments of the present invention provide systems and method for improving platform dump collection. The method includes upon receiving a platform dump request for a system, accessing a model of the system hardware and a list of commands for the dump. The method further includes determining whether a constraint exists for the command in the list, identifying which software and hardware locks are required by the constraints, determining whether a hardware and software lock is required by multiple constraints, generating a grouping of the constraints requiring the hardware and software lock, and generating an executable list of commands.Type: GrantFiled: September 15, 2016Date of Patent: May 7, 2019Assignee: International Business Machines CorporationInventors: Nagendra K. Gurram, Deepak Kodihalli
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Patent number: 10248470Abstract: A method, executed by a computer, includes locking a system mutex of a system target, locking a node group with a single node group write-lock, wherein the node group comprises a plurality of nodes that are all locked by the single node group write-lock, and wherein each node of the plurality of nodes has a plurality of descendants, and locking the plurality of descendants corresponding to a node with a single node write-lock. A computer system and computer program product corresponding to the above method are also disclosed herein.Type: GrantFiled: August 31, 2016Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventor: Deepak Kodihalli
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Patent number: 10241875Abstract: An approach for at least one service processor to receive a notification of at least one failure during an initial program load of a server and to identify at least one step failing the initial program load. The at least one service processor determines whether a set of conditions are met to switch the initial program load responsibility from a master processor to a service processor. Furthermore, responsive to the at least one service processor determining that the set of one or more conditions are met to switch initial program load responsibility, the at least one service processor assumes the initial program load responsibility.Type: GrantFiled: September 15, 2016Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Manish K. Chowdhary, Raja Das, Nagendra K. Gurram, Deepak Kodihalli
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Publication number: 20180309736Abstract: Disclosed aspects relate to symmetric multiprocessing (SMP) management. A first SMP topology may be identified by a service processor firmware. The first SMP topology may indicate a first set of connection paths for a plurality of processor chips of a multi-node server. A second SMP topology may be identified by the service processor firmware. The second SMP topology may indicate a second set of connection paths for the plurality of processor chips of the multi-node server. The second SMP topology may differ from the first SMP topology. An error event related to the first SMP topology may be detected. A set of traffic may be routed using the second SMP topology. The set of traffic may be routed by the service processor firmware in response to detecting the error event related to the first SMP topology.Type: ApplicationFiled: June 27, 2018Publication date: October 25, 2018Inventors: Deepak Kodihalli, Venkatesh Sainath, Dhruvaraj Subhashchandran
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Publication number: 20180152422Abstract: Disclosed aspects relate to symmetric multiprocessing (SMP) management. A first SMP topology may be identified by a service processor firmware. The first SMP topology may indicate a first set of connection paths for a plurality of processor chips of a multi-node server. A second SMP topology may be identified by the service processor firmware. The second SMP topology may indicate a second set of connection paths for the plurality of processor chips of the multi-node server. The second SMP topology may differ from the first SMP topology. An error event related to the first SMP topology may be detected. A set of traffic may be routed using the second SMP topology. The set of traffic may be routed by the service processor firmware in response to detecting the error event related to the first SMP topology.Type: ApplicationFiled: November 30, 2016Publication date: May 31, 2018Inventors: Deepak Kodihalli, Venkatesh Sainath, Dhruvaraj Subhashchandran
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Publication number: 20180074921Abstract: An approach for at least one service processor to receive a notification of at least one failure during an initial program load of a server and to identify at least one step failing the initial program load. The at least one service processor determines whether a set of conditions are met to switch the initial program load responsibility from a master processor to a service processor. Furthermore, responsive to the at least one service processor determining that the set of one or more conditions are met to switch initial program load responsibility, the at least one service processor assumes the initial program load responsibility.Type: ApplicationFiled: September 15, 2016Publication date: March 15, 2018Inventors: Manish K. Chowdhary, Raja Das, Nagendra K. Gurram, Deepak Kodihalli
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Publication number: 20180074882Abstract: Embodiments of the present invention provide systems and method for improving platform dump collection. The method includes upon receiving a platform dump request for a system, accessing a model of the system hardware and a list of commands for the dump. The method further includes determining whether a constraint exists for the command in the list, identifying which software and hardware locks are required by the constraints, determining whether a hardware and software lock is required by multiple constraints, generating a grouping of the constraints requiring the hardware and software lock, and generating an executable list of commands.Type: ApplicationFiled: September 15, 2016Publication date: March 15, 2018Inventors: Nagendra K. Gurram, Deepak Kodihalli
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Publication number: 20180060141Abstract: A method, executed by a computer, includes locking a system mutex of a system target, locking a node group with a single node group write-lock, wherein the node group comprises a plurality of nodes that are all locked by the single node group write-lock, and wherein each node of the plurality of nodes has a plurality of descendants, and locking the plurality of descendants corresponding to a node with a single node write-lock. A computer system and computer program product corresponding to the above method are also disclosed herein.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventor: Deepak Kodihalli
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Publication number: 20180052746Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology in response to determining that the first processor is directed connected to an oscillator. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure, the system re-configures to the second TOD topology.Type: ApplicationFiled: October 31, 2017Publication date: February 22, 2018Inventors: Manish Kumar Chowdhary, Deepak Kodihalli
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Patent number: 9886357Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure requiring a topology switch, the system re-configures to the second TOD topology.Type: GrantFiled: October 11, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Manish Kumar Chowdhary, Deepak Kodihalli
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Patent number: 9804938Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure requiring a topology switch, the system re-configures to the second TOD topology.Type: GrantFiled: November 2, 2015Date of Patent: October 31, 2017Assignee: International Business Machines CorporationInventors: Manish Kumar Chowdhary, Deepak Kodihalli
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Publication number: 20170103004Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure requiring a topology switch, the system re-configures to the second TOD topology.Type: ApplicationFiled: October 11, 2015Publication date: April 13, 2017Inventors: Manish Kumar Chowdhary, Deepak Kodihalli
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Publication number: 20170103005Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure requiring a topology switch, the system re-configures to the second TOD topology.Type: ApplicationFiled: November 2, 2015Publication date: April 13, 2017Inventors: Manish Kumar Chowdhary, Deepak Kodihalli