Patents by Inventor DEEPAK KUMAR AGARWAL

DEEPAK KUMAR AGARWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11809220
    Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: November 7, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Deepak Kumar Agarwal, Kunal Desai, Jimit Shah, Rakesh Gehalot
  • Publication number: 20230342241
    Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Inventors: DEEPAK KUMAR AGARWAL, Kunal DESAI, Jimit SHAH, Rakesh GEHALOT