Abstract: In described examples, an R2R digital-to-analog converter includes multiple arms and a voltage regulator. Respective arms include an arm switch with a p-channel MOSFET (PFET) switch and an n-channel MOSFET (NFET) switch. The voltage regulator includes a differential amplifier, a p-ladder that includes N cascade-coupled PFETS and has first and second ends, an n-ladder that includes y×N cascade-coupled NFETS and has first and second ends, a first resistor (resistance R), and a second resistor (resistance y×R). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. A second terminal of the second resistor is coupled to the first n-ladder end. An output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage of the NFET switch.

Abstract: A circuit includes a digital-to-analog converter and a gain stage. The gain stage includes: an operational amplifier; a variable gain network; and a leakage current control circuit. A first input of the operational amplifier is coupled to an input of the gain stage. An output of the operational amplifier is coupled to an output of the gain stage. A first terminal of the variable gain network is coupled to the second input of the operational amplifier. A second terminal of the variable gain network is coupled to the output of the operational amplifier. A first terminal of the leakage current control circuit is coupled to the output of the operational amplifier. A second terminal of the leakage current control circuit coupled to a third terminal of the variable gain network.

Abstract: In described examples, an R2R digital-to-analog converter includes multiple arms and a voltage regulator. Respective arms include an arm switch with a p-channel MOSFET (PFET) switch and an n-channel MOSFET (NFET) switch. The voltage regulator includes a differential amplifier, a p-ladder that includes N cascade-coupled PFETS and has first and second ends, an n-ladder that includes y×N cascade-coupled NFETS and has first and second ends, a first resistor (resistance R), and a second resistor (resistance y×R). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. A second terminal of the second resistor is coupled to the first n-ladder end. An output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage of the NFET switch.

Abstract: In described examples, a test control circuit includes a subsystem and a transition control circuit. The subsystem outputs test signals to, and receives and measures response signals of, a device under test (DUT). The transition control circuit operates the test control circuit in response to a first operational state information indicating a first mode and a first set of configuration settings; receives a Transition Trigger signal and a second operational state information indicating a second mode and a second set of configuration settings; and, by performing allowed mode changes and in response to receiving the Transition Trigger signal, transitions the test control circuit to operating in response to the second operational state information. Allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.

Abstract: A circuit includes a digital-to-analog converter and a gain stage. The gain stage includes: an operational amplifier; a variable gain network; and a leakage current control circuit. A first input of the operational amplifier is coupled to an input of the gain stage. An output of the operational amplifier is coupled to an output of the gain stage. A first terminal of the variable gain network is coupled to the second input of the operational amplifier. A second terminal of the variable gain network is coupled to the output of the operational amplifier. A first terminal of the leakage current control circuit is coupled to the output of the operational amplifier. A second terminal of the leakage current control circuit coupled to a third terminal of the variable gain network.

Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.

Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.

Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.

Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.

Abstract: An active voltage regulator circuit having improved wake-up response is presented. The circuit includes an op-amp whose output is connected to a pass device for supplying the output level, and has both capacitive and resistive parts in its feedback loop. When the regulator is enabled, the capacitive elements are initially connected, followed after a delay by the resistive elements of the feedback loop.

Abstract: An active voltage regulator circuit having improved wake-up response is presented. The circuit includes an op-amp whose output is connected to a pass device for supplying the output level, and has both capacitive and resistive parts in its feedback loop. When the regulator is enabled, the capacitive elements are initially connected, followed after a delay by the resistive elements of the feedback loop.