Abstract: An apparatus including: a MIMO antenna for transmitting beamformed signals on a plurality of beams using a common frequency- and time-limited physical channel resource; circuitry for computing a beamforming gain of each beam in each sub-sector in a coverage area of said plurality of beams; circuitry for determining a beam dominance region of each beam within the coverage area of said plurality of beams; circuitry for determining, within the dominance region of each beam, an average of the beamforming gain of each of the other beams at least partially co-locating within said beam dominance region; circuitry for determining inter-beam interference estimations as an average interference of each beam from each of said other beams; and circuitry for scheduling transmissions of the beams by said MIMO antenna on said common frequency- and time-limited physical channel resource based on said inter-beam interference estimations.

Abstract: Beam and antenna array split configuration optimization is disclosed. A network node device generates a beam dictionary defining a set of beams. The network node device estimates a traffic density distribution for a radio channel based on obtained channel quality information. The network node device determines, for each of at least two array split configurations associated with a transceiver antenna array of the network node device, a set of optimal beams from the beam dictionary that optimizes a utility function, based on the estimated traffic density distribution. The network node device selects an array split configuration that maximizes the utility function across a coverage area of a radio cell associated with the network node device. The network node device applies the selected array split configuration to the transceiver antenna array in response to evaluating that the selected array split configuration improves downlink performance.

Abstract: An apparatus comprising: a MIMO antenna for transmitting beamformed signals on a plurality of beams using a common frequency- and time-limited physical channel resource; means for computing a beamforming gain of each beam in each sub-sector in a coverage area of said plurality of beams; means for determining a beam dominance region of each beam within the coverage area of said plurality of beams; means for determining, within the dominance region of each beam, an average of the beamforming gain of each of the other beams at least partially co-locating within said beam dominance region; means for determining inter-beam interference estimations as an average interference of each beam from each of said other beams; and means for scheduling transmissions of the beams by said MIMO antenna on said common frequency- and time-limited physical channel resource based on said inter-beam interference estimations.

Abstract: A solution for allocating N radio beam configurations to access nodes including, in some embodiments, a method comprising storing a beam library defining a set of radio beam configurations for a coverage area. A coverage area is divided into sub-areas, and a set of channel quality metrics is collected, as is a traffic density parameter for each sub-area. The following steps are performed: selecting N radio beam configurations from the set of radio beam configurations; mapping each sub-area with one of the selected N radio beam configurations; computing a service performance for the selected N radio beam configurations; the service performance is weighted by the traffic density parameters. The service performance are stored as linked to each radio beam configuration of the selected N radio beam configurations. Based on the stored service performances, a set of N radio beam configurations is selected and the N radio beam configurations are allocated.

Abstract: A solution for allocating N radio beam configurations to access nodes including, in some embodiments, a method comprising storing a beam library defining a set of radio beam configurations for a coverage area. A coverage area is divided into sub-areas, and a set of channel quality metrics is collected, as is a traffic density parameter for each sub-area. The following steps are performed: selecting N radio beam configurations from the set of radio beam configurations; mapping each sub-area with one of the selected N radio beam configurations; computing a service performance for the selected N radio beam configurations; the service performance is weighted by the traffic density parameters. The service performance are stored as linked to each radio beam configuration of the selected N radio beam configurations. Based on the stored service performances, a set of N radio beam configurations is selected and the N radio beam configurations are allocated.

Abstract: In some embodiments, a computing system maintains, in a memory, information on one or more terminal devices, a dictionary of beams and information on a spatial grid. The computing system maps each terminal device to the spatial grid based on up-to-date results of radio measurements and calculates, for each spatial element, a load caused by the one or more terminal devices based on the mapping. The computing system evaluates, for each combination of a beam and a terminal device, a reference signal received power, RSRP, based on results of the radio measurements. The computing system calculates a first map of expected spatial distribution of traffic based on the calculated loads and beam-specific second maps of expected RSRP based on the values of the RSRP. Finally, the computing system causes performing beamforming optimization based on the first map and second maps.

Abstract: In some embodiments, a computing system maintains, in a memory, information on one or more terminal devices, a dictionary of beams and information on a spatial grid. The computing system maps each terminal device to the spatial grid based on up-to-date results of radio measurements and calculates, for each spatial element, a load caused by the one or more terminal devices based on the mapping. The computing system evaluates, for each combination of a beam and a terminal device, a reference signal received power, RSRP, based on results of the radio measurements. The computing system calculates a first map of expected spatial distribution of traffic based on the calculated loads and beam-specific second maps of expected RSRP based on the values of the RSRP. Finally, the computing system causes performing beamforming optimization based on the first map and second maps.

Abstract: Methods, systems, and computer-readable media for taxonomy generation with automated analysis and auditing are disclosed. A primary classification is determined for a hierarchical taxonomy of items in a marketplace. The primary classification is selected from a plurality of terms describing items in the marketplace, and the primary classification is selected based at least in part on automated analysis of the terms. A plurality of secondary classifications are determined for the hierarchical taxonomy. The secondary classifications are selected from the terms describing the items in the marketplace, and the secondary classifications are selected based at least in part on automated analysis of the terms. The hierarchical taxonomy is modified based at least in part on feedback from a plurality of users. The feedback comprises one or more terms entered by one or more of the users to filter a set of items.

Abstract: A technology for determining accuracy estimates for classifications used in an electronic catalog. In one example, classifications for product groupings included in an electronic catalog may be updated as a result of the classifications inaccurately representing products included in the product groupings. The electronic catalog of products may be grouped into a plurality of product groupings using classifications. Classifications of product groupings that inaccurately represent products included in the product grouping may be updated with suggested classifications. Update metrics for updates made to the grouping classifications may be collected and the update metrics may be used to calculate an accuracy estimate for the classifications used in the electronic catalog.

Abstract: Techniques are provided herein for utilizing a classification engine to improve a classification model. For example, a classification engine may derive a statistical model based at least in part on a synthetic data set. A misclassification may be determined based at least in part on an output of the statistical model. An audit question may be provided to an individual, the audit question being determined based at least in part on the determined misclassification. Response data related to the audit question may be received. The statistical model may be validated based at least in part on the response data.

Abstract: At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device. A substrate is formed. A strained relaxed layer is formed on the substrate. A first tensile strained layer is formed on the strained relaxed layer. A first compressive strain layer is formed on the first tensile strained layer.

Abstract: At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device. A substrate is formed. A strained relaxed layer is formed on the substrate. A first tensile strained layer is formed on the strained relaxed layer. A first compressive strain layer is formed on the first tensile strained layer.

Abstract: A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the channel region of the semiconductor device. The semiconductor device further includes first and second trenches formed adjacent to the gate stack, where the first and second trenches are conically shaped to be wider at a top portion of each trench as compared to a width of each trench below the top portion of each trench. The semiconductor device further includes strained silicon alloy formed within the first and second trenches, where a stress force exerted on the channel region of the semiconductor device is maximized at a surface of the semiconductor device below the gate stack.

Abstract: An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

Abstract: A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallographic directions, but exhibit an etch rate that is much slower in a second crystallographic direction. As such, one dimension of the etching process is time controlled, a second dimension of the etching process is self-aligned using sidewall spacers of the gate stack, and a third dimension of the etching process is inherently controlled by the selective etch phenomenon of the selective etchant along the second crystallographic direction. A deeper trench is implemented by first forming a lightly doped drain (LDD) region under the gate stack and using the sidewall spacers in combination with the LDD regions to deepen the trenches formed within the semiconductor material.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.

Abstract: Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.