Abstract: A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.

Abstract: A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.

Abstract: A system and method for restoring the arrival order of a plurality of packets after receipt of the packets and prior to a retransmission of the plurality of packets are provided. The invented system is configured to process a first number of packets through a high latency path, and then process all remaining packets through a lower latency path. The received packets are stored after processing in a queue memory until either (a.) all of the packets processed through the high latency path are fully processed through the high latency path, or (b.) a time period of packet processing has expired. The packets stored in the queue are transmitted from the system in the order in which the packets were received by the system, and the additional data packets are retransmitted without storage in the queue memory.

Abstract: A system and method for enabling one or more memories to maintain, update, and provide counter values. In a first version a dynamic random access memory, or DRAM, is bi-directionally communicatively coupled with a processor. The DRAM is divided into a plurality of banks. In the first version a set of subcounters is established, wherein each subcounter element is separately and singly located within a different DRAM bank. The value of a counter can be derived by reading and processing, e.g., adding, all of the values of each of an assigned set of subcounter subvalues maintained within the plurality of banks. Conversely, a counter value may be updated by updating a single assigned subcounter of a single bank. The first method allows a hosting computer to select a subcounter having a shortest access time, where the subcounter is an element of a set of subcounters assigned to maintain a given counter value.