Patents by Inventor Deepak Mehta

Deepak Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160140301
    Abstract: Computer-implemented methods and systems for validating digital surgical videos are disclosed herein. According to an embodiment, an Internet-based method for validating a digital video comprises submitting the digital surgical video to a video hosting website; analyzing and accepting the video for a pre-publication review, wherein the pre-publication review comprises automatically assigning the accepted video to at least two randomly selected reviewers using a computer algorithm; automatically associating an approved for publication status identifier with the video; and embedding an indicia representative of validation of the video content in the approved for publication video.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 19, 2016
    Inventors: Gresham T. Richter, Deepak Mehta
  • Publication number: 20130214763
    Abstract: Used electric energy is collected while maintaining accuracy. Information to be displayed on a display 14 is generated in such a way that a gateway 4 processes a measured value (with a time stamp) transmitted from a power meter 2, an appliance monitor 5, a solar module 10, and a battery center 13 through a wireless LAN. In the gateway 4, the used electric energy is synchronized with each other by the time stamp. Further, an integrated value of the used electric energy in the time direction is calculated. The information can be secured by obtaining the integrated value of data even if breakdown of devices and the like due to power failure occurs.
    Type: Application
    Filed: June 29, 2011
    Publication date: August 22, 2013
    Applicant: SONY CORPORATION
    Inventors: Eiichiro Kubota, Antonio Avitabile, Costantino Cristiano Mariella, Christopher Michael Rutherford, Edward Grellier Colby, Nicholas George Bailey, Alexander Charles Knill, Harshul Deepak Mehta
  • Publication number: 20130214608
    Abstract: To solve problems arising when a power conditioner equivalent to that connected to a solar panel is connected to a power storage device. Direct-current power generated by the solar panel 9 is supplied to a DC-DC converter 51 and output as a predetermined direct-current voltage. The output voltage of the converter 51 is supplied to a DC-AC inverter 52. Direct-current power generated by the power storage device 11 is supplied to a DC-DC converter 55. Predetermined direct-current power from the converter 55 is supplied to a DC-AC inverter 56. Alternating-current power output by the inverter 56 is supplied to an alternating-current power system at home. The converter 55 is configured to have two output voltages. The first output voltage is a standby voltage. The second voltage is a voltage at which the inverter 56 starts power supply to outside.
    Type: Application
    Filed: June 29, 2011
    Publication date: August 22, 2013
    Applicant: SONY CORPORATION
    Inventors: Eiichiro Kubota, Antonio Avitabile, Costantino Mariella, Christopher Rutherford, Edward Colby, Nicholas George Bailey, Alexander Charles Knill, Harshul Deepak Mehta
  • Patent number: 8164345
    Abstract: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: April 24, 2012
    Assignee: Rutgers, The State University of New Jersey
    Inventors: Michael L. Bushnell, Raghuveer Ausoori, Omar Khan, Deepak Mehta, Xinghao Chen
  • Publication number: 20110019594
    Abstract: A method of configuring a feature subscription having the steps of: a) retrieving a feature subscription, the feature subscription comprising one or more features; b) configuring the feature subscription; c) determining one or more consistent solutions of the feature subscription configured in step b); and d) selecting a consistent solution from the one or more consistent solutions determined in step c).
    Type: Application
    Filed: March 25, 2009
    Publication date: January 27, 2011
    Applicant: BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
    Inventors: David Lesaint, Deepak A. Mehta, Luis O. Quesada Ramirez, Barry A. O'Sullivan, Peter N. Wilson
  • Publication number: 20100102825
    Abstract: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF.
    Type: Application
    Filed: May 18, 2009
    Publication date: April 29, 2010
    Applicant: Rutgers, The State University of New Jersey
    Inventors: Michael L. Bushnell, Raghuveer Ausoori, Omar Khan, Deepak Mehta, Xinghao Chen
  • Patent number: 7549198
    Abstract: A new and improved sealed joint or system is disclosed for securing together the opposite ends of plastic strapping, which is encircled around the package or bale, in order to ensure that the opposite ends of the plastic strapping do not exhibit any slipping or relative movement with respect to each other whereby the predeterminedly formed size or shape of the package or bale is able to be preserved or maintained. In accordance with various different embodiments of the present invention, different arrangements of the sealed joint, with respect to the opposite ends of the plastic strapping, are structured whereby enhanced frictional contact is effectively developed between the sealed joint and the opposite ends of the plastic strapping, or between the opposite ends of the plastic strapping per se, so as to in fact reduce the amount of slipperiness effectively defined between the opposite ends of the plastic strapping.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 23, 2009
    Assignee: Illinois Tool Works Inc.
    Inventors: Anatoly Gosis, Donald L. Van Erden, Deepak Mehta, Manuel Enriquez, Abram Cervantes, Penmetesa N. Varma
  • Patent number: 7197438
    Abstract: A memory compiler characterization system and method for determining parametric data, wherein memory compilers of a first type are rigorously characterized and memory compilers of a second type are sparsely characterized with respect to a particular parameter. Absolute scale factors are determined based on the ratio of the parametric data points of two congruent memory compilers, one from each type. Interpolated scale factors are obtained based on the absolute scale factors. Parametric data for the remaining compilers of the sparsely characterized compiler set is filled out by applying the interpolated scale factors in conjunction with the data of the congruent memory compilers of the first type.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: March 27, 2007
    Assignee: Virage Logic Corp.
    Inventors: Deepak Mehta, Andrew Knight, Deepak Sabharwal, Raymond Tak-Hoi
  • Publication number: 20060168768
    Abstract: A new and improved sealed joint or system is disclosed for securing together the opposite ends of plastic strapping, which is encircled around the package or bale, in order to ensure that the opposite ends of the plastic strapping do not exhibit any slipping or relative movement with respect to each other whereby the predeterminedly formed size or shape of the package or bale is able to be preserved or maintained. In accordance with various different embodiments of the present invention, different arrangements of the sealed joint, with respect to the opposite ends of the plastic strapping, are structured whereby enhanced frictional contact is effectively developed between the sealed joint and the opposite ends of the plastic strapping, or between the opposite ends of the plastic strapping per se, so as to in fact reduce the amount of slipperiness effectively defined between the opposite ends of the plastic strapping.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Inventors: Anatoly Gosis, Donald Van Erden, Deepak Mehta, Manuel Enriquez, Abram Cervantes, P.N. Varma
  • Publication number: 20050263233
    Abstract: An over-molded fitment is configured for mounting to a flexible packaging material. The fitment includes a flange having first and second sides, a spout extending upwardly from the first side of the flange and an over-molded sealing media molded onto the first side of the flange. The flange and spout are integral with one another and formed from a single first material. The over-molded sealing media is formed from a second material different from the first material and having a density less than a density of the first material. The sealing media permits joining the different materials of the flexible packaging and the fitment that would otherwise not seal to one another. A method for forming the over-molded fitment and a package formed with the fitment are also disclosed.
    Type: Application
    Filed: May 6, 2005
    Publication date: December 1, 2005
    Inventors: Terrence Meier, James Zielinski, Jeffrey Stupar, Deepak Mehta
  • Publication number: 20040051189
    Abstract: An over-molded fitment is configured for mounting to a flexible packaging material. The fitment includes a flange having first and second sides, a spout extending upwardly from the first side of the flange and an over-molded sealing media molded onto the first side of the flange. The flange and spout are integral with one another and formed from a single first material. The over-molded sealing media is formed from a second material different from the first material and having a density less than a density of the first material. The sealing media permits joining the different materials of the flexible packaging and the fitment that would otherwise not seal to one another. A method for forming the over-molded fitment and a package formed with the fitment are also disclosed.
    Type: Application
    Filed: July 15, 2003
    Publication date: March 18, 2004
    Inventors: Terrence P. Meier, James S. Zielinski, Jeffrey M. Stupar, Deepak Mehta
  • Patent number: 5637366
    Abstract: Polyester-containing multilayer biaxially-oriented polypropylene films are provided. According to the invention, a two- or three-layer polyester-containing cap layer is bonded to a monoaxially oriented polypropylene core, followed by orientation of the resulting composite in a direction transverse to the direction of orientation of the core layer. At least one tie layer is interposed between the core and the polyester. Advantageously, the polyester contains silicone fluid as a processing aid.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 10, 1997
    Assignee: QPF, Inc. (Delaware Corporation)
    Inventors: Alan M. Davis, John Lawrence, Deepak Mehta