Abstract: Methods and apparatus for training a neural network to detect living beings in an enclosed space are disclosed. An example method includes obtaining channel state information (CSI) data based at least in part on a sequence of signals received at one or more receivers located in the enclosed space, generating training data for the neural network based at least in part on the CSI data, training the neural network using the training data to detect living beings in the enclosed space, and processing the trained neural network for deployment.

Abstract: A machine learning accelerator includes a scalable processor with a plurality of cores that receive data from system memory via a system direct memory access (DMA) engine. Each core may include local memory, a compute sub-system, and one or more slices, each of which includes a descriptor execution engine and one or more compute engines. Each compute engine includes input data memory, one or more sub-compute engines, and partial data memory. The sub-compute engines are separately connected to the input data memory and are configured to independently perform compute operations, such as multiply-accumulate (MAC) operations, on the input data and to provide partial output data to the partial data memory. The cores, slices and sub-compute engines may be configured to operate independently to perform separate tasks in parallel that once completed are combined as part of a large artificial intelligence model.

Abstract: Methods and apparatus are disclosed for joint optimization of machine learning model architecture and quantization. An example method includes generating a first machine learning model for a resource-constrained device based on quantized outputs from each of a plurality of compute blocks. Each compute block includes a plurality of inverted residual blocks coupled in series. Determining the quantized output of each respective compute block includes performing a first convolution, based at least in part on a first quantization level, on input data to a first inverted residual block, performing a second convolution on an output of the first convolution based at least in part on the first quantization level, adding an output of the second convolution to the input data to generate a first quantized output, and providing the first quantized output to a second inverted residual block, and providing the first machine learning model to the resource-constrained device for execution.

Abstract: This disclosure provides methods, devices, and systems for computer vision. The present implementations more specifically relate to automated data collection and annotation of store items at the point of sale. In some implementations, a computer vision system may capture one or more images of an object via one or more cameras each having a field of view (FOV) that encompasses a sensing region of a checkout counter; receive information about the object from a point of sale (POS) system associated with the sensing region, the information including at least a price of the object; and training the computer vision model to classify objects in the sensing region of the checkout counter based on the one or more images captured via the one or more cameras and the information received from the POS system.

Abstract: A method, apparatus, and system are discussed to efficiently process and execute Artificial Intelligence operations. An integrated circuit has a tailored architecture to process and execute Artificial Intelligence operations, including computations for a neural network having weights with a sparse value. The integrated circuit contains at least a scheduler, one or more arithmetic logic units, and one or more random access memories configured to cooperate with each other to process and execute these computations for the neural network having weights with the sparse value.

Abstract: An artificial intelligence processor can optimize the usage of its neural network to process a data set more efficiently. The artificial intelligence processor can have a neural network of multiple arithmetic logic units each having one or more computing engines and a local arithmetic memory divided into a set of clusters arranged into a node ring. A scheduler with a local scheduler memory for each cluster. An advanced extensible interface can read a data set model from an external memory in a single data read. A memory manager can control the node ring. When a data size of the data set is larger than a processing model layer for processing the data set, the memory manager can slice the data set into data set chunks. The memory manager can assign a data set chunk to a data cluster. The memory manager can broadcast channel instructions from the processing model layer to every cluster.

Abstract: An integrated circuit with a neural network can reduce the number of accesses off circuit by embedding a dedicated processor for each cluster in a neural network. The integrated circuit has a neural network of multiple arithmetic logic units arranged in clusters. Each arithmetic logic unit have one or more computing engines and a local arithmetic memory. The integrated circuit can associate a scheduler with each cluster. The integrated circuit can associate a cluster local memory with each cluster. The integrated circuit can associate a dedicated embedded processor with each cluster. The dedicated embedded processor is capable of performing general purpose operations. The integrated circuit can execute a non-computational operation offloaded from the cluster.

Abstract: An artificial intelligence processor can optimize the usage of its neural network to reduce the need to access external memory during operations. The artificial intelligence processor can have multiple arithmetic logic units each configured to have one or more computing engines to perform the computations for the AI system. A set of schedulers are each configured to have a local scheduler memory. A memory manager is configured to execute an instruction set from a compiler. The compiler is configured to divide the multiple arithmetic logic units into multiple clusters. The compiler is configured to assign each cluster a scheduler from the set of schedulers. The scheduler is configured to cooperate with a memory manager so that a fetch of data from an external memory to the local scheduler memory occurs a single time per calculation.

Abstract: A method, apparatus, and system are discussed to efficiently process and execute Artificial Intelligence operations. An integrated circuit has a tailored architecture to process and execute Artificial Intelligence operations, including computations for a neural network having weights with a sparse value. The integrated circuit contains at least a scheduler, one or more arithmetic logic units, and one or more random access memories configured to cooperate with each other to process and execute these computations for the neural network having weights with the sparse value.

Abstract: A method, apparatus, and system are discussed to efficiently process and execute Artificial Intelligence operations. An integrated circuit has a tailored architecture to process and execute Artificial Intelligence operations, including computations for a neural network having weights with a sparse value. The integrated circuit contains at least a scheduler, one or more arithmetic logic units, and one or more random access memories configured to cooperate with each other to process and execute these computations for the neural network having weights with the sparse value.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified packet based on threads of instructions, each thread of instructions corresponding to a context received from the scheduler. The modified packet is generated before queuing the packet for transmission as an output packet of the network processor, and the packet modifier processes instructions for generating the modified packet in the order in which the contexts were generated for each flow, without head-of-line blocking between flows.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: Described embodiments provide an input/output interface of a network processor that generates a request to store received packets to a system cache. If an entry associated with the received packet does not exist in the system cache, the system cache determines whether a backpressure indicator of the system cache is set. If the backpressure indicator is set, the received packet is written to the shared memory. If the backpressure indicator is not set, the system cache determines whether to evict data from the system cache in order to store the received packet. If an eviction rate of the system cache has reached a threshold, the system cache sets a backpressure indicator and writes the received packet to the shared memory. If the eviction rate has not reached the threshold, the system cache determines an available entry and writes the received packet to the available entry in the system cache.

Abstract: Described embodiments process hash operation requests of a network processor. A hash processor determines a job identifier, a corresponding hash table, and a setting of a traversal indicator for a received hash operation request that includes a desired key. The hash processor concurrently generates a read request for a first bucket of the hash table, and provides the job identifier, the key and the traversal indicator to a read return processor. The read return processor stores the key and traversal indicator in a job memory and stores, in a return memory, entries of the first bucket of the hash table. If a stored entry matches the desired key, the read return processor determines, based on the traversal indicator, whether to read a next bucket of the hash table and provides the job identifier, the matching key, and the address of the bucket containing the matching key to the hash processor.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and maintains a thread status table and a sequence counter for each flow. Active threads are tracked by the thread status table, and each status entry includes a sequence value and a flow value identifying the flow. Each sequence counter generates a sequence value for each thread by incrementing the sequence counter each time processing of a thread for the associated flow is started, and decrementing the sequence counter each time a thread for the associated flow is completed.

Abstract: Described embodiments process multiple threads of commands in a network processor. One or more tasks are generated corresponding to each received packet, and the tasks are provided to a packet processor module (MPP). A scheduler associates each received task with a command flow. A thread updater writes state data corresponding to the flow to a context memory. The scheduler determines an order of processing of the command flows. When a processing thread of a multi-thread processor is available, the thread updater loads, from the context memory, state data for at least one scheduled flow to one of the multi-thread processors. The multi-thread processor processes a next command of the flow based on the loaded state data. If the processed command requires operation of a co-processor module, the multi-thread processor sends a co-processor request and switches command processing from the first flow to a second flow.

Abstract: Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.