Abstract: Apparatus and method for thread dispatch throttle control. For example, an example processor comprises: a plurality of graphics cores to execute instructions of a plurality of compute threads; and dispatch circuitry to dispatch each compute thread for execution on a graphics core of the plurality of graphics cores, the dispatch circuitry to track a number of compute threads of the plurality of compute threads dispatched to each graphics core of the plurality of graphics cores which have not completed; the dispatch circuitry to adjust a dispatch throttling threshold value based on stall metrics associated with each graphics core of the plurality of graphics cores, the stall metrics including a number of cycles for which the one or more compute threads of the plurality of compute threads are stalled within a clock window.

Abstract: Quantum-based dispatch of workgroups is described. An example of an apparatus includes a computer memory to store data for processing, including data for an application; and one or more processors including a graphical processing unit (GPU), the GPU including multiple chiplets, each of the multiple chiplets including compute containers and a cache, each compute container including a plurality of processing resources, and a dispatcher for dispatching workgroups to the processing resources of the GPU, wherein dispatching workgroups includes dispatching workgroups for the application according to a selected workgroup quantum, the selected workgroup quantum having a certain size and shape.

Abstract: Apparatus and method for throttling ray tracing operations based on a cache hit rate. For example, one embodiment of a processor comprises: a cache subsystem comprising one or more caches; circuitry to track a plurality of hits and misses in the cache subsystem for data accesses associated with ray tracing operations; and thread management logic to dynamically control a working set size for the ray tracing operations based on the plurality of hits and misses.

Abstract: Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.