Patents by Inventor Deepak Nayak
Deepak Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210320709Abstract: Systems, methods, apparatuses, and computer program products for determining a grid-of-beams (GoB) are provided. One method may include collecting network data for training a neural network, train the neural network, using the collected data, to learn a non-discounted cumulative reward Q that evaluates a benefit of including a given beam into a grid-of-beams (GoB), iteratively applying the trained neural network to select at least one optimal beam to include in the grid-of-beams (GoB), and selecting one or more beams from the grid-of-beams (GoB) to transmit to a user equipment or to receive transmission from the user equipment.Type: ApplicationFiled: September 13, 2018Publication date: October 14, 2021Inventors: Deepak NAYAK, Chandrashekhar THEJASWI, Suresh KALYANASUNDARAM, Rajeev AGRAWAL, Hua XU, Anand BEDEKAR, Veronique CAPDEVIELLE, Claudiu MIHAILESCU, Boris KOUASSI, Afef FEKI
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Publication number: 20210182137Abstract: Systems and methods for adaptive fault prediction analysis are described. In one embodiment, the system includes one or more computing components, and one or more hardware controllers. In some embodiments, the storage system includes a storage drive. At least one of the one or more hardware controllers is configured to analyze one or more tolerance limits of a first computing component among the plurality of computing components; calculate a failure metric of the first computing component based at least in part on the analysis of the one or more tolerance limits of the first computing component; analyze sensor data from the first computing component in real time; and update the failure metric based at least in part on the analyzing of the sensor data.Type: ApplicationFiled: March 2, 2021Publication date: June 17, 2021Inventors: Deepak NAYAK, Hemant MOHAN
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Publication number: 20210152231Abstract: A method is described of selecting, by a multi-antenna base station of a wireless communications system, at least one transmission beam to transmit data to at least one terminal. The method can include determining a grid of N2 transmission beams intended to cover a portion of the space served by the base station and generated by using N1 antennas of the base station, where N1 and N2 designate integers such as N2>N1, and selecting one or more non-adjacent beam(s) of the grid to transmit data to at least one terminal during at least one given time interval.Type: ApplicationFiled: November 13, 2020Publication date: May 20, 2021Inventors: Zwi Altman, Deepak Nayak, Suresh Kalyanasundaram, Philippe Sehier
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Patent number: 10976795Abstract: A power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to enable temporary power to be provided from the at least one energy storage device to a plurality of data storage devices upon a system power loss event. The power controller is further configured to receive a power loss indication signal associated with any individual one of the plurality of data storage devices and responsively enable power loss protection for the data storage device.Type: GrantFiled: April 30, 2019Date of Patent: April 13, 2021Assignee: Seagate Technology LLCInventors: Deepak Nayak, Hemant Mohan, Rajesh Maruti Bhagwat
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Patent number: 10970146Abstract: Systems and methods for adaptive fault prediction analysis are described. In one embodiment, the system includes one or more computing components, and one or more hardware controllers. In some embodiments, the storage system includes a storage drive. At least one of the one or more hardware controllers is configured to analyze one or more tolerance limits of a first computing component among the plurality of computing components; calculate a failure metric of the first computing component based at least in part on the analysis of the one or more tolerance limits of the first computing component; analyze sensor data from the first computing component in real time; and update the failure metric based at least in part on the analyzing of the sensor data.Type: GrantFiled: March 9, 2018Date of Patent: April 6, 2021Assignee: SEAGATE TECHNOLOGY LLCInventors: Deepak Nayak, Hemant Mohan
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Patent number: 10847994Abstract: A system includes a direct current uninterruptible power supply (DC UPS) that receives an alternating current (AC) power input and provides a first DC power output. The system also includes a power distribution unit (PDU). The PDU receives the first DC power output from the DC UPS. The PDU converts the first DC power output into a second DC power output that supplies power to at least one component of information technology equipment (ITE) via a DC mating connector.Type: GrantFiled: March 15, 2019Date of Patent: November 24, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Hemant Mohan, Deepak Nayak, Rajesh Maruti Bhagwat
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Publication number: 20200348742Abstract: A power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to enable temporary power to be provided from the at least one energy storage device to a plurality of data storage devices upon a system power loss event. The power controller is further configured to receive a power loss indication signal associated with any individual one of the plurality of data storage devices and responsively enable power loss protection for the data storage device.Type: ApplicationFiled: April 30, 2019Publication date: November 5, 2020Inventors: Deepak Nayak, Hemant Mohan, Rajesh Maruti Bhagwat
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Patent number: 10784402Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.Type: GrantFiled: March 27, 2019Date of Patent: September 22, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Srinivasa Banna, Deepak Nayak
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Publication number: 20200295591Abstract: A system includes a direct current uninterruptible power supply (DC UPS) that receives an alternating current (AC) power input and provides a first DC power output. The system also includes a power distribution unit (PDU). The PDU receives the first DC power output from the DC UPS. The PDU converts the first DC power output into a second DC power output that supplies power to at least one component of information technology equipment (ITE) via a DC mating connector.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Inventors: Hemant Mohan, Deepak Nayak, Rajesh Maruti Bhagwat
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Publication number: 20190278648Abstract: Systems and methods for adaptive fault prediction analysis are described. In one embodiment, the system includes one or more computing components, and one or more hardware controllers. In some embodiments, the storage system includes a storage drive. At least one of the one or more hardware controllers is configured to analyze one or more tolerance limits of a first computing component among the plurality of computing components; calculate a failure metric of the first computing component based at least in part on the analysis of the one or more tolerance limits of the first computing component; analyze sensor data from the first computing component in real time; and update the failure metric based at least in part on the analyzing of the sensor data.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Applicant: SEAGATE TECHNOLOGY LLCInventors: Deepak NAYAK, Hemant MOHAN
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Patent number: 10396121Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.Type: GrantFiled: August 18, 2017Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
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Patent number: 10388691Abstract: A color stacked light emitting diode (LED) pixel is disclosed. The color stacked LED includes an LED pixel structure body, a base LED disposed on at least a portion of the LED pixel structure body, an intermediate LED disposed on the base LED, and a top LED disposed on the intermediate LED. The stacked LED may be an overlapping or a non-overlapping LED pixel. The LED pixel structure body may be a fin body or a nanowire body.Type: GrantFiled: May 18, 2017Date of Patent: August 20, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Srinivasa Banna, Deepak Nayak, Ajey P. Jacob
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Publication number: 20190221708Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.Type: ApplicationFiled: March 27, 2019Publication date: July 18, 2019Inventors: Srinivasa BANNA, Deepak NAYAK
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Patent number: 10290768Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.Type: GrantFiled: September 14, 2017Date of Patent: May 14, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Srinivasa Banna, Deepak Nayak
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Patent number: 10283560Abstract: Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an LED with first and second terminals while the second substrate surface includes CMOS circuit components. The CMOS components and LED are coupled by through silicon via (TSV) contacts which extend through the second substrate surface.Type: GrantFiled: February 20, 2018Date of Patent: May 7, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Deepak Nayak, Srinivasa Banna, Ajey P. Jacob
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Patent number: 10263151Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.Type: GrantFiled: August 18, 2017Date of Patent: April 16, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
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Patent number: 10249710Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.Type: GrantFiled: July 18, 2017Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Steven Bentley, Deepak Nayak
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Publication number: 20190081206Abstract: Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.Type: ApplicationFiled: September 14, 2017Publication date: March 14, 2019Inventors: Srinivasa BANNA, Deepak NAYAK
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Publication number: 20190058002Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak
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Publication number: 20190058087Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Ajey P. Jacob, Srinivasa Banna, Deepak Nayak