Abstract: A controlled start-up circuit mechanism in a linear voltage regulator can handle a higher supply voltage at start-up and limits the voltage seen at the devices to be lower than the maximum allowed operation voltage. The circuit may regulate voltage for operating a device coupled to a host when the host supply exceeds that necessary for device operation. The controlled start-up mechanism handles a sudden ramp up or spike of supply voltage relative to the device's operational voltage.

Abstract: A process detection circuit can detect process information in both PMOS and NMOS devices without external components or trimming. The process detection circuit may be able to identify process information on a gate-source voltage (VGS) that represents process effects. Identified process information may be used to optimize system on a chip (SoC) operation.

Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.

Abstract: An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.

Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Abstract: A proposed inrush control circuit may work in the presence of supply noise. A linear regulator in bypass mode may be designed for inrush current control, but may be susceptible to irregularities from increased supply noise. The circuit may include a splitting of the bypass power MOS that are switched on with some delay during the power on to control the initial power-on inrush current.

Abstract: A capacitor from a Metal-Oxide-Metal (“MoM”) process may include a plurality of metal layers arranged with different design structures. The metal layers may be connected with vias. The metal layers may include wires, such as rows and/or fingers that are arranged for maximizing capacitance between adjacent fingers, as well as between fingers of different metal layers. As the spacing of the fingers is increased, the reliability, yield of final product, and ease of manufacturing both increase. The capacitor increases the spacing of wires/fingers while either maintaining or improving the capacitance per unit area.

Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.

Abstract: A buck power converter creates a desired output voltage from a greater input voltage with higher efficiency than linear regulators or charge pumps. For compact-size and cost sensitive products, the use of the buck power converter is hindered mainly because of lack of physical space and increases in the cost of the passive components like the inductor and capacitor. Techniques are presented to reduce the sizes of the passive components so that they can be integrated on-chip or in-package or on board. A signal converter in the buck power converter determines the duty cycle of a switching control signal. The switching control signal would ordinarily have driven a power switching circuit that provides current to the inductor in the buck power converter. The signal converter outputs a modified (multiphase) switching control signal that includes multiple separated on-periods that taken together approximate the duty cycle of the switching control signal while maintaining the same control loop frequency.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: A low drop-out (LDO) voltage regulation circuit includes first and second internal current paths. The first internal current path is between the input supply voltage and ground and includes the regulator's buffer circuit. The second internal current path is between the input supply voltage and ground and includes the regulator's power transistor. The amount of current flowing through the first internal current path relative to the amount of current flowing through the second internal current path is an increasing function of a current supplied to a load connected to the output supply node. The load regulation of the LDO is improved as the DC gain will not go down at lower load currents. Further, the no load to full load response time is improved as the load pole and power MOS gate pole are actively controlled with respect to output load current.

Abstract: An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller.

Abstract: An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.

Abstract: An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.

Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Abstract: A low drop-out (LDO) voltage regulation circuit includes first and second internal current paths. The first internal current path is between the input supply voltage and ground and includes the regulator's buffer circuit. The second internal current path is between the input supply voltage and ground and includes the regulator's power transistor. The amount of current flowing through the first internal current path relative to the amount of current flowing through the second internal current path is an increasing function of a current supplied to a load connected to the output supply node. The load regulation of the LDO is improved as the DC gain will not go down at lower load currents. Further, the no load to full load response time is improved as the load pole and power MOS gate pole are actively controlled with respect to output load current.