Patents by Inventor Deepak Raghu

Deepak Raghu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10379754
    Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.
    Type: Grant
    Filed: January 20, 2018
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Philip David Reusswig, Nian Niles Yang, Grishma Shah, Deepak Raghu, Preeti Yadav, Prasanna Desai Sudhir Rao, Smita Aggarwal, Dana Lee
  • Patent number: 10373696
    Abstract: A method for writing data to a NAND flash memory is disclosed, having steps of writing a first set of data to a first memory block, writing a second set of data to a second memory block, writing a third set of data to a third memory block and writing a fourth set of data to a XNOR memory block.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Gautam Ashok Dusija, Aaron Lee, Mrinal Kochar, Deepak Raghu
  • Publication number: 20190238640
    Abstract: A data management services architecture includes architectural components that run in both a storage and compute domains. The architectural components redirect storage requests from the storage domain to the compute domain, manage resources allocated from the compute domain, ensure compliance with a policy that governs resource consumption, deploy program code for data management services, dispatch service requests to deployed services, and monitor deployed services. The architectural components also include a service map to locate program code for data management services, and service instance information for monitoring deployed services and dispatching requests to deployed services. Since deployed services can be stateless or stateful, the services architecture also includes state data for the stateful services, with supporting resources that can expand or contract based on policy and/or service demand. The architectural components also include containers for the deployed services.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Deepak Raghu Kenchammana-Hosekote, Shiva Chaitanya, Saeed Ghanbari, Barry Patrick Benight, David Anthony Slik
  • Publication number: 20190238641
    Abstract: A data management services architecture includes architectural components that run in both a storage and compute domains. The architectural components redirect storage requests from the storage domain to the compute domain, manage resources allocated from the compute domain, ensure compliance with a policy that governs resource consumption, deploy program code for data management services, dispatch service requests to deployed services, and monitor deployed services. The architectural components also include a service map to locate program code for data management services, and service instance information for monitoring deployed services and dispatching requests to deployed services. Since deployed services can be stateless or stateful, the services architecture also includes state data for the stateful services, with supporting resources that can expand or contract based on policy and/or service demand. The architectural components also include containers for the deployed services.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Deepak Raghu Kenchammana-Hosekote, Shiva Chaitanya, Saeed Ghanbari, Barry Patrick Benight, David Anthony Slik
  • Publication number: 20190057750
    Abstract: A method for writing data to a NAND flash memory is disclosed, having steps of writing a first set of data to a first memory block, writing a second set of data to a second memory block, writing a third set of data to a third memory block and writing a fourth set of data to a XNOR memory block.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 21, 2019
    Inventors: Gautam Ashok DUSIJA, Aaron Lee, Mrinal Kochar, Deepak Raghu
  • Publication number: 20180309852
    Abstract: I/O bandwidth reduction using storage-level common page information is implemented by a storage server, in response to receiving a request from a client for a page stored at a first virtual address, determining that the first virtual address maps to a page that is a duplicate of a page stored at a second virtual address or that the first and second virtual addresses map to a deduplicated page within a storage system, and transmitting metadata to the client mapping the first virtual address to a second virtual address that also maps to the deduplicated page. For one embodiment, the metadata is transmitted in anticipation of a request for the redundant/deduplicated page via the second virtual address. For an alternate embodiment, the metadata is sent in response to a determination that a page that maps to the second virtual address was previously sent to the client.
    Type: Application
    Filed: June 22, 2018
    Publication date: October 25, 2018
    Inventors: Deepak Raghu KENCHAMMANA-HOSEKOTE, Michael R. EISLER, Arthur F. LENT, Rohul IYER, Shravan GAONKAR
  • Patent number: 10102920
    Abstract: A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. The read thresholds in the read retry table may be used to avoid errors caused by shifting of charge levels. The optimization of read retry includes weighting or reordering of the read retry cases in the read retry table. The selection of a read retry case (and corresponding read thresholds) are determined based on the weighting or reordering.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 16, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Philip Reusswig, Deepak Raghu, Zelei Guo, Chris Nga Yee Yip
  • Patent number: 10026488
    Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 17, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Phil Reusswig, Joanna Lai, Deepak Raghu, Grishma Shah, Nian Niles Yang
  • Patent number: 10025661
    Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 17, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Pitamber Shukla, Joanna Lai, Henry Chin, Deepak Raghu, Abhilash Kashyap
  • Patent number: 10021218
    Abstract: I/O bandwidth reduction using storage-level common page information is implemented by a storage server, in response to receiving a request from a client for a page stored at a first virtual address, determining that the first virtual address maps to a page that is a duplicate of a page stored at a second virtual address or that the first and second virtual addresses map to a deduplicated page within a storage system, and transmitting metadata to the client mapping the first virtual address to a second virtual address that also maps to the deduplicated page. For one embodiment, the metadata is transmitted in anticipation of a request for the redundant/deduplicated page via the second virtual address. For an alternate embodiment, the metadata is sent in response to a determination that a page that maps to the second virtual address was previously sent to the client.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: July 10, 2018
    Assignee: NetApp Inc.
    Inventors: Deepak Raghu Kenchammana-Hosekote, Michael R. Eisler, Arthur F. Lent, Rahul Iyer, Shravan Gaonkar
  • Publication number: 20180181462
    Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Pitamber Shukla, Joanna Lai, Henry Chin, Deepak Raghu, Abhilash Kashyap
  • Patent number: 10007311
    Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 26, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Deepak Raghu, Pao-Ling Koh, Philip Reusswig, Chris Nga Yee Yip, Jun Wan, Yan Li
  • Publication number: 20180143772
    Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.
    Type: Application
    Filed: January 20, 2018
    Publication date: May 24, 2018
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: PHILIP DAVID REUSSWIG, NIAN NILES YANG, GRISHMA SHAH, DEEPAK RAGHU, PREETI YADAV, PRASANNA DESAI SUDHIR RAO, SMITA AGGARWAL, DANA LEE
  • Publication number: 20180053562
    Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.
    Type: Application
    Filed: August 18, 2016
    Publication date: February 22, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Phil Reusswig, Joanna Lai, Deepak Raghu, Grishma Shah, Nian Niles Yang
  • Publication number: 20180046231
    Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 15, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Deepak Raghu, Pao-Ling Koh, Philip Reusswig, Chris Nga Yee Yip, Jun Wan, Yan Li
  • Publication number: 20180046527
    Abstract: A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. The read thresholds in the read retry table may be used to avoid errors caused by shifting of charge levels. The optimization of read retry includes weighting or reordering of the read retry cases in the read retry table. The selection of a read retry case (and corresponding read thresholds) are determined based on the weighting or reordering.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 15, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Philip Reusswig, Deepak Raghu, Zelei Guo, Chris Nga Yee Yip
  • Patent number: 9880752
    Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: January 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Philip David Reusswig, Nian Niles Yang, Grishma Shah, Deepak Raghu, Preeti Yadav, Prasanna Desai Sudhir Rao, Smita Aggarwal, Dana Lee
  • Patent number: 9842114
    Abstract: A technique described herein performs peer to peer network write deduplication. A host system generates a fingerprint for data associated with a write request. The host system may then determine whether the generated fingerprint matches a local fingerprint stored in a local data structure or whether the generated fingerprint matches a global fingerprint associated with a global data structure, wherein the local fingerprint is associated with data previously written to the storage system by the host and wherein the global fingerprint is associated with data previously written to the storage system by a different host. If a match is found, the host system constructs a deduplication command utilizing a logical address corresponding to a storage location that stores the data. If a match is not found, a write command for the data of the write request is constructed and sent to the storage system.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 12, 2017
    Assignee: NetApp, Inc.
    Inventors: Deepak Raghu Kenchammana-Hosekote, Anshul Madan
  • Patent number: 9785357
    Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Deepak Raghu, Chris Aviala, Harish Singidi, Guirong Liang, Anne Pao-Ling Koh, Dana Lee, Gautam Dusija
  • Publication number: 20170262191
    Abstract: In order to reduce write tail latency, a storage system generates redundant write requests when performing a storage operation for an object. The storage operation is determined to be effectively complete when a minimum number of write requests have completed. For example, the storage system may generate twelve write requests and also generate four redundant write requests for a total of sixteen write requests. The storage system considers the object successfully stored once twelve of the sixteen writes complete successfully. To generate the redundant writes, the storage system may use replication or erasure coding. For replication, the storage system may issue a redundant write request for each of n chunks being written. For erasure coding, the storage system may use rateless codes which can generate unlimited number of parity chunks or use an n+k+k' erasure code which generates an additional k encoded chunks, in place of an n+k erasure code.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 14, 2017
    Inventors: Suganthi Dewakar, Xing Lin, Junji Zhi, Deepak Raghu Kenchammana-Hosekote