Patents by Inventor Deepak Samuel Kirubakaran
Deepak Samuel Kirubakaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972303Abstract: Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also includes a selector to select between the first compute block and the second compute block for assignment of the workload. The selection is based on which of the first and second predicted temperatures is lower. The apparatus further includes a workload scheduler to assign the workload to the selected one of the first or second compute blocks.Type: GrantFiled: June 26, 2020Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Carin Ruiz, Bo Qiu, Columbia Mishra, Arijit Chattopadhyay, Chee Lim Nge, Srikanth Potluri, Jianfang Zhu, Deepak Samuel Kirubakaran, Akhilesh Rallabandi, Mark Gallina, Renji Thomas, James Hermerding, II
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Patent number: 11934249Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.Type: GrantFiled: March 31, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Zhongsheng Wang, Chris Binns, Deepak Samuel Kirubakaran, Ashraf H Wadaa, Rajshree Chabukswar, Ahmed Shams, Sze Ling Yeap, Refael Mizrahi, Nicholas Klein
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Publication number: 20240045490Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.Type: ApplicationFiled: August 15, 2023Publication date: February 8, 2024Inventors: Jianfang Zhu, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
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Patent number: 11775047Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.Type: GrantFiled: August 2, 2022Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Jianfang Zhu, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
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Patent number: 11733761Abstract: Methods and apparatus to manage power and performance of computing devices based on user presence are disclosed. An apparatus includes an engagement detector to determine an engagement of a user with a device based on at least one of image data generated by an image sensor or an application running on the device; and an operation mode selector to select one of a plurality of operation modes for the device based on a level of engagement of the user, the plurality of operation modes including (1) a first operation mode associated with the device operating at a first performance level and a first power level and (2) a second operation mode associated with the device operating at a second performance level and a second power level, the first performance level being higher than the second performance level, the first power level being higher than the second power level.Type: GrantFiled: December 27, 2019Date of Patent: August 22, 2023Assignee: INTEL CORPORATIONInventors: Vishal Sinha, Paul Diefenbaugh, Kristoffer Fleming, Raoul Rivas Toledano, Deepak Samuel Kirubakaran, William Braun
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Publication number: 20220374066Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.Type: ApplicationFiled: August 2, 2022Publication date: November 24, 2022Inventors: JIANFANG ZHU, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
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Patent number: 11422849Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.Type: GrantFiled: August 22, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Deepak Samuel Kirubakaran, Vijay Dhanraj, Russell Jerome Fenger, Hisham Abu-Salah, Eliezer Weissmann
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Patent number: 11422616Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.Type: GrantFiled: March 26, 2020Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Jianfang Zhu, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
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Publication number: 20220221925Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.Type: ApplicationFiled: March 31, 2022Publication date: July 14, 2022Inventors: Zhongsheng Wang, Chris Binns, Deepak Samuel Kirubakaran, Ashraf H Wadaa, Rajshree Chabukswar, Ahmed Shams, Sze Ling Yeap, Refael Mizrahi, Nicholas Klein
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Publication number: 20220188016Abstract: An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.Type: ApplicationFiled: December 21, 2021Publication date: June 16, 2022Inventors: Jianwei Dai, Virendra Vikramsinh Adsure, Taeyoung Kim, Chia-Hung S. Kuo, Deepak Gandiga Shivakumar, Amir Ali Radjai, Deepak Samuel Kirubakaran, Jianfang Zhu, Ivan Chen
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Patent number: 11354213Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.Type: GrantFiled: August 27, 2018Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Hisham Abu Salah, Arthur Leonard Brown, Russell J. Fenger, Deepak Samuel Kirubakaran, Asit K. Mallick, Jun Pan, Srinivas Pandruvada, Efraim Rotem, Arjan Van De Ven, Eliezer Weissmann, Rafal J. Wysocki
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Publication number: 20220113781Abstract: Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Jianwei Dai, Jianfang Zhu, Ivan Chen, Deepak Samuel Kirubakaran, Rajshree Chabukswar, Richard Winterton, Houfei Chen
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Publication number: 20220114136Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Jianfang Zhu, Ivan Chen, Barnes Cooper, Jianwei Dai, Martin Dixon, Kristoffer Fleming, Mark Gallina, Duncan Glendinning, Deepak Samuel Kirubakaran, Chia-Hung S. Kuo, Yifan Li, Adam Norman, Michael Rosenzweig, Kai P Wang, Jin Yan, Virendra Vikramsinh Adsure
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Publication number: 20220058029Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.Type: ApplicationFiled: December 22, 2020Publication date: February 24, 2022Applicant: Intel CorporationInventors: Noor Mubeen, Ashraf H. Wadaa, Andrey Gabdulin, Russell Fenger, Deepak Samuel Kirubakaran, Marc Torrant, Ryan Thompson, Georgina Saborio Dobles, Lingjing Zeng
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Publication number: 20210303054Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: JIANFANG ZHU, DEEPAK SAMUEL KIRUBAKARAN, RAOUL RIVAS TOLEDANO, CHEE LIM NGE, RAJSHREE CHABUKSWAR, JAMES HERMERDING, II, SUDHEER NAIR, WILLIAM BRAUN, ZHONGSHENG WANG, RUSSELL FENGER, UDAYAN KAPALEY
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Publication number: 20210304096Abstract: Techniques and mechanisms to dynamically prioritize communication of a data flow based on an indication of a user's interest in a particular task. In an embodiment, data flows correspond to different respective tasks that are executed with a host operating system. An output of a human interface device indicates whether, at a particular time, a user of a computer device is interested in one particular task over another task. Where greater user interest in a first task is indicated, a first packet type corresponding to the first task is assigned a relatively high priority, as compared to a second packet type which corresponds to a second task. Based on the priority, a resource of the network interface is selectively made available (or prevented from being made available) for the communication of a given packet. In another embodiment, the resource includes a queue of the network interface.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Deepak Samuel Kirubakaran, Venkateshan Udhayan, Atsuo Kuwahara, Rajshree Chabukswar, Ramakrishnan Sivakumar, William Braun, Noam Ginsburg, Jianfeng Zhu, Paul Diefenbaugh, Kristoffer Fleming, Keerthanna Mohan
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Publication number: 20210294641Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Applicant: Intel CorporationInventors: Deepak Samuel Kirubakaran, William A. Braun, Rajshree A. Chabukswar, Leigh Davies, Russell J. Fenger, Alexander Gendler, Raoul V. Rivas Toledano, Eliezer Weissmann
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Publication number: 20210109585Abstract: Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes an image sensor. The example computing device further includes wireless communication circuitry. The example computing device also includes an operations controller to cause the wireless communication circuitry to switch between different operation modes based on an analysis of image data generated by the image sensor. Different ones of the operation modes to consume different amounts of power.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Kristoffer Fleming, Melanie Daniels, Paul Diefenbaugh, Aleksander Magi, Lawrence Falkenstein, Raoul Rivas Toledano, Vishal Sinha, Deepak Samuel Kirubakaran, Venkateshan Udhayan, Marko Bartscherer, Kathy Bui
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Publication number: 20210055958Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Deepak Samuel Kirubakaran, Vijay Dhanraj, Russell Jerome Fenger, Hisham Abu-Salah, Eliezer Weissmann
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Publication number: 20200326994Abstract: Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also includes a selector to select between the first compute block and the second compute block for assignment of the workload. The selection is based on which of the first and second predicted temperatures is lower. The apparatus further includes a workload scheduler to assign the workload to the selected one of the first or second compute blocks.Type: ApplicationFiled: June 26, 2020Publication date: October 15, 2020Inventors: Carin Ruiz, Bo Qiu, Columbia Mishra, Arijit Chattopadhyay, Chee Lim Nge, Srikanth Potluri, Jianfang Zhu, Deepak Samuel Kirubakaran, Akhilesh Rallabandi, Mark Gallina, Renji Thomas, James Hermerding II