Patents by Inventor Deepak Thimmegowda
Deepak Thimmegowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230200063Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Deepak Thimmegowda, Chang Wan Ha, Md Rezaul Karim Nishat, Liu Liu, Yuanrong Shui, Kwame Eason, Ahmed Reza, Hoon Koh
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Patent number: 11653496Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.Type: GrantFiled: September 25, 2020Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Chang Wan Ha, Chuan Lin, Deepak Thimmegowda, Zengtao Liu, Binh N. Ngo, Soo-yong Park
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Publication number: 20230076831Abstract: An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 8, 2021Publication date: March 9, 2023Applicant: Intel CorporationInventors: Praveen Kumar Kalsani, Ahmed Reza, Liu Liu, Deepak Thimmegowda, Zengtao Tony Liu, Sriram Balasubrahmanyam
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Publication number: 20230036595Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.Type: ApplicationFiled: February 8, 2020Publication date: February 2, 2023Inventors: Deepak THIMMEGOWDA, Brian J. CLEEREMAN, Srivardhan GOWDA, Jui-Yen LIN, Liu LIU, Krishna PARAT, Jong Sun SEL, Baosuo ZHOU
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Publication number: 20220399057Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 9, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Chang Wan Ha, Deepak Thimmegowda, Hoon Koh, Richard M. Gularte, Liu Liu, David Meyaard, Ahsanur Rahman
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Publication number: 20220359554Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 11424256Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: GrantFiled: October 24, 2019Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Patent number: 11398489Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: GrantFiled: September 4, 2020Date of Patent: July 26, 2022Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 11393716Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: July 31, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20220102365Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Chang Wan HA, Chuan LIN, Deepak THIMMEGOWDA, Zengtao LIU, Binh N. NGO, Soo-yong PARK
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Publication number: 20210005624Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: ApplicationFiled: September 4, 2020Publication date: January 7, 2021Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Publication number: 20200365452Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 10804280Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.Type: GrantFiled: September 5, 2018Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Khaled Hasnat, Prashant Majhi, Deepak Thimmegowda
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Patent number: 10770470Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: GrantFiled: March 13, 2017Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 10748811Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: April 8, 2019Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20200227525Abstract: A driver circuit for a three-dimensional (3D) memory device has a field management structure electrically coupled to a gate conductor. The field management structure causes an electric field peak in a vertical channel of the 3D memory device when a voltage differential exists between the source conductor and the drain conductor and the gate conductor is not biased. The electrical field peak can adjust the electrical response of the driver circuit, enabling the circuit to have a higher breakdown threshold voltage and improved drive current. Thus, the driver circuit can enable a scalable vertical string driver that is above the memory array instead of under the memory array circuitry.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Dong JI, Guangyu HUANG, Deepak THIMMEGOWDA
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Publication number: 20200227429Abstract: A driver circuit for a three-dimensional (3D) memory device has a super junction structure as a field management structure. The super junction structure could be referred to as an extended junction structure, which distributes the electrical field of the junction between the vertical channel and the gate conductor for a string driver. The vertical channel includes a channel conductor to connect vertically between a source conductor and a drain conductor. The extended junction structure extends in parallel with the vertical channel conductor, extending vertically toward the drain conductor, having a height greater than a height of the gate conductor.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Dong JI, Guangyu HUANG, Deepak THIMMEGOWDA
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Publication number: 20200152650Abstract: Embodiments of the present disclosure are directed towards a memory device with a split staircase, in accordance with some embodiments. In one embodiment, the memory device includes one or more pillars disposed in a die, and a plurality of wordlines formed in a stack of multiple tiers and coupled with the one or more pillars. At least some of the wordlines are split across the tiers into at least first and second portions. Respective ends of at least some wordlines of at least one of the first or second portions, at a location of the split, are exposed to provide electrical coupling with other components of the device. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 8, 2018Publication date: May 14, 2020Inventors: Deepak Thimmegowda, Owen Jungroth, Khaled Hasnat, David Meyaard, Surendranath C. Eruvuru
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Patent number: 10593624Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.Type: GrantFiled: July 25, 2018Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Deepak Thimmegowda, Aaron Yip, Mark Helm, Yongna Li
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Publication number: 20200058662Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: ApplicationFiled: October 24, 2019Publication date: February 20, 2020Applicant: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie