Abstract: Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.

Abstract: A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.

Abstract: Active and passive electronic components are placed on a substrate and encapsulated with mold material to produce a molded core substrate for fabricating a hybrid integrated circuit (IC) device. A carrier has a release film laminated to a face thereof. A seed layer of copper is added over the release film and fiducials are plated onto the copper seed layer for component placement using alignment marks on the fiducials. Mold material is applied to the encapsulation layer and around and over the components. Mold material is ground planar with component tops. The carrier and release film are removed, leaving the copper seed layer exposed, which is etched to a pattern. Holes are formed in the mold material and then surfaces thereof are copper plated. A multilayer dielectric film is laminated over copper plating. Vias are formed in the multilayer dielectric film for connections to components.

Abstract: Disclosed herein is a chip package assembly that includes a package substrate coupled with an integrated circuit die, a stiffener attached to a top surface of the package substrate, and a connector assembly integrated with the stiffener. Both the connector assembly and the stiffener are disposed at a peripheral area of the top surface. The connector assembly includes a bracket and a connector. The connector is configured to connect with one or more optical cables or electrical connectors. The bracket may be formed by a cavity in the stiffener. The bracket may be attached to the top surface of the package substrate. The stiffener may be coupled with the bracket directly or via the connector. Additionally, a frame coupled to the stiffener or a PCB board may be used to secure the bracket in place.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.

Abstract: A chip package having a package substrate including a top surface. A first chip module and a second chip module are mounted above the top surface of the package substrate. A first interposer is disposed between the package substrate and the first and second chip modules and includes a glass interposer. The first interposer couples the first and second chip modules to the package substrate. An interconnect bridge is disposed in a cavity of the glass interposer. The interconnect bridge includes circuitry that connects a circuitry of the first chip module to a circuitry of the second chip module.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: Chip packages are described herein that includes chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes voltage regulation circuitry that is coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.

Abstract: The disclosed inductor includes a magnetic material surrounding a conductive core. The magnetic material and conductive core can be embedded in a substrate. The magnetic material and conductive core can be formed in the substrate, using a magnetic composite material. Various other systems and methods are also disclosed.

Abstract: A method for forming a core for a substrate that removes portions of a resist layer based on a pattern specifying widths of removed portions of the resist layer. The method forms a set of pillars by plating the remaining portions of the resist layer with a conductive material, so each pillar of the set has a perimeter plated with the conductive material. Additionally, each pillar of the set of pillars is encapsulated with a dielectric material. In some implementations, the dielectric material is an organic material.

Abstract: A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second plated through-hole on the second surface of the component. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An apparatus and method for efficiently transferring information as signals through a silicon package substrate. A semiconductor fabrication process (or process) begins with a relatively thin package substrate core layer and uses lasers to create openings in the package substrate at locations of the signal routes. The use of each of the relatively thin core layer and the lasers allows for reduction in the pitch of the signal routes. The process creates signal routes in the openings using stacked vias from one side of the package substrate to an opposite side of the package substrate. Additionally, the process forms the package substrate with multiple embedded passive components with different thicknesses in different layers of the package substrate. The embedded passive components are used to improve signal integrity of the signal routes.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.