Patents by Inventor Deepak Vinayak KADETOTAD

Deepak Vinayak KADETOTAD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROCESSOR ARRAY FOR PROCESSING SPARSE BINARY NEURAL NETWORKS
    Publication number: 20230297819
    Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i?1 layer of the binary neural network.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Inventors: Ram KRISHNAMURTHY, Gregory K. CHEN, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL, Deepak Vinayak KADETOTAD
  • Processor array for processing sparse binary neural networks
    Patent number: 11663452
    Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i?1 layer of the binary neural network.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Ram Krishnamurthy, Gregory K. Chen, Raghavan Kumar, Phil Knag, Huseyin Ekin Sumbul, Deepak Vinayak Kadetotad
  • PROCESSOR ARRAY FOR PROCESSING SPARSE BINARY NEURAL NETWORKS
    Publication number: 20200019847
    Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i?1 layer of the binary neural network.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Ram KRISHNAMURTHY, Gregory K. CHEN, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL, Deepak Vinayak KADETOTAD