Patents by Inventor Deepal Wehella-Gamage
Deepal Wehella-Gamage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10707217Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.Type: GrantFiled: May 24, 2018Date of Patent: July 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricardo A. Donaton, Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage
-
Publication number: 20180337185Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.Type: ApplicationFiled: May 24, 2018Publication date: November 22, 2018Inventors: Ricardo A. DONATON, Babar A. KHAN, Xinhui WANG, Deepal WEHELLA-GAMAGE
-
Patent number: 10037998Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.Type: GrantFiled: April 7, 2017Date of Patent: July 31, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricardo A. Donaton, Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage
-
Patent number: 9893086Abstract: A method of forming a contact to mitigate punch through in SOI substrates is disclosed. The method may include providing an active region in SOI substrate isolated from another region in the SOI substrate by a shallow trench isolation (STI), the active region having a silicided source/drain region adjacent the STI. A spacer may be formed at an edge of the silicided source/drain region adjacent to the STI. A contact etch stop layer (CESL) may be deposited over the spacer and a dielectric layer over the CESL. A contact opening may be formed to the source/drain region through the CESL and the dielectric layer. A portion of the contact opening is positioned over the spacer such that the spacer prevents punch through into the STI. A contact may then be formed in the contact opening.Type: GrantFiled: November 16, 2016Date of Patent: February 13, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Kasun Anupama Gardiye Punchihewa, Deepal Wehella-Gamage
-
Publication number: 20170213835Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Inventors: Ricardo A. DONATON, Babar A. KHAN, Xinhui WANG, Deepal WEHELLA-GAMAGE
-
Patent number: 9679917Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.Type: GrantFiled: December 23, 2014Date of Patent: June 13, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricardo A. Donaton, Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage
-
Publication number: 20160181249Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming a plurality of fin structures from a substrate material. The method further includes forming a deep trench capacitor structure, contacting at least selected fin structures. The method further includes forming a liner over the deep trench capacitor structure. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structure protecting the deep trench capacitor structure during deposition and etching processes.Type: ApplicationFiled: December 17, 2014Publication date: June 23, 2016Inventors: Guillaume D. BRIEND, Ricardo A. DONATON, Herbert L. HO, Donghun KANG, Babar A. KHAN, Xinhui WANG, Deepal WEHELLA-GAMAGE
-
Publication number: 20160181253Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Ricardo A. DONATON, Babar A. KHAN, Xinhui WANG, Deepal WEHELLA-GAMAGE
-
Patent number: 9324430Abstract: A method of generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.Type: GrantFiled: April 30, 2014Date of Patent: April 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sheikh Sabiq Chishti, Toshiaki Kirihata, Krishnan S. Rengarajan, Deepal Wehella-Gamage
-
Publication number: 20150318043Abstract: A method generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: International Business Machines CorporationInventors: Sheikh Sabiq Chishti, Toshiaki Kirihata, Krishnan S. Rengarajan, Deepal Wehella-Gamage
-
Patent number: 8546219Abstract: Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.Type: GrantFiled: October 13, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Deepal Wehella-Gamage, Viorel Ontalus
-
Publication number: 20130095619Abstract: Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deepal Wehella-Gamage, Viorel Ontalus
-
Publication number: 20080157200Abstract: The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material. Considering that the facet in the prior art is due to an STI divot formed during several necessary wet etching processes, the MOSFET source/drain edge of the inventive structure is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material. As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Applicant: International Business Machines CorporationInventors: Byeong Y. Kim, Shahid A. Butt, Xiaomeng Chen, Shwu-Jen J. Jeng, Hasan M. Nayfeh, Deepal Wehella-Gamage