Abstract: A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Abstract: A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.

Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.

Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.

Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.

Abstract: A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.