Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully hardwired performance levels. This invention achieves hardwired image pipe processing performance but offers full flexibility and programmability of software achieving the best of both hardwired and software image pipes processing.

Abstract: A video processing front-end for digital cameras, camcorders, video cell phones, et cetera has multiple interconnected processing modules for functions such as CCD controller, preview engine, auto exposure, auto focus, auto white balance, et cetera with complicated data flow can be realized and managed.

Abstract: A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38).

Abstract: A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully hardwired performance levels. This invention achieves hardwired image pipe processing performance but offers full flexibility and programmability of software achieving the best of both hardwired and software image pipes processing.

Abstract: A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.

Abstract: A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.

Abstract: A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38).

Abstract: Tetrahedral interpolation by rewriting the interpolation in terms of ordered differentials and color differences to lower the computational complexity. Additionally, hardward architecture allows efficient implementation.