Patents by Inventor Deepika Thumsi Umesh

Deepika Thumsi Umesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735247
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Gitanjali T. Ghosh, Debra M. Bell, Arunmozhi R. Subramaniam, Roya Baghi, Deepika Thumsi Umesh, Sue-Fern Ng
  • Publication number: 20220172768
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventors: Gitanjali T. Ghosh, Debra M. Bell, Arunmozhi R. Subramaniam, Roya Baghi, Deepika Thumsi Umesh, Sue-Fern Ng
  • Patent number: 11270757
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gitanjali T. Ghosh, Debra M. Bell, Arunmozhi R. Subramaniam, Roya Baghi, Deepika Thumsi Umesh, Sue-Fern Ng
  • Publication number: 20210201981
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.
    Type: Application
    Filed: September 15, 2020
    Publication date: July 1, 2021
    Inventors: Gitanjali T. Ghosh, Debra M. Bell, Arunmozhi R. Subramaniam, Roya Baghi, Deepika Thumsi Umesh, Sue-Fern Ng