Patents by Inventor Deepthi Amuru

Deepthi Amuru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250384296
    Abstract: The present invention discloses a Unified Deep-Learning Neural Network (U-DNN) Architecture capable of modeling a wide range of AMS circuits effectively and shows the ways it can be used for on demand circuit specification, design optimization and self-adaptation. Applying the U-DNN architecture for analog circuit characterization demonstrated consistent performance across all the DUTs, with an R2Score exceeding 0.95 with {?E,?E}<1% for the test split data, validating its accuracy. The U-DNN architecture exhibited an average MaPE of less than 1% over unseen test cases, showcasing its strong generalization capabilities. Remarkably, the knowledge encapsulated in the U-DNN architecture, gained from modeling diverse AMS circuits in CMOS 180 nm and 65 nm technologies, translated into accurate modeling of AMS circuits in CMOS 28 nm.
    Type: Application
    Filed: June 18, 2025
    Publication date: December 18, 2025
    Inventors: DEEPTHI AMURU, ZIA ABBAS, KHANH MINH LE
  • Publication number: 20240394451
    Abstract: A method and system based on machine learning to create self-adapting analog circuits adapted to change their internal components on-the-fly in response to changes in process, voltage, and temperature to re-tune the electrical characteristics back to nominal specified values is disclose. The method and system herein comprise of designing the analog circuit, generating simulation data for machine learning, creating a full query database, creating and training, using simulation results, a machine learning (ML) model of the circuit and applying the ML model to infer the required changes to internal components of the analog circuit in response to changes in P, V, and T conditions. With this method and system, evaluation of the adverse effects of PVT changes, decision on internal circuit changes, and realization of requisite design changes are performed by the computer system solely within a ML data domain, in a time and resource efficient manner.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Inventors: Zia Abbas, Khanh Minh Le, Koushik De, Deepthi Amuru
  • Publication number: 20230153597
    Abstract: An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.
    Type: Application
    Filed: May 27, 2022
    Publication date: May 18, 2023
    Inventors: Koushik De, Khanh Minh Le, Deepthi Amuru, Zia Abbas
  • Patent number: 11416664
    Abstract: The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: August 16, 2022
    Assignee: Analog Intelligent Design, Inc.
    Inventors: Khanh M Le, Koushik De, Deepthi Amuru, Zia Abbas
  • Publication number: 20210182466
    Abstract: The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions.
    Type: Application
    Filed: November 3, 2020
    Publication date: June 17, 2021
    Inventors: Khanh M Le, Koushik De, Deepthi Amuru, Zia Abbas