Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.