Abstract: A set of techniques are disclosed for organizing an electronic memory to increase the effective decoding speed while being able to randomly address storage locations in the memory. The memory typically contains a memory array (41 or 51) and address circuitry (40 or 50). In one memory-organization technique, the address circuitry contains a group of decoding segments (50.sub.1 -50.sub.M) arranged in series. Each decoding segment partially decodes an input memory address. In another memory-organization technique, the address circuitry contains a plurality of decoding segments (40.sub.1 and 40.sub.2) arranged in parallel, each decoding segment sequentially decoding different ones of the input memory addresses than each other decoding segment. A variation of the parallel memory-organization technique can be used with off-the-shelf memories.