Abstract: A renaming unit configured to rename source operands of instructions in a group. A renaming register maintains architectural to physical register mappings. Architectural to physical register mappings propagate from the renaming register through a chain of update units (U) over bus lines denoted with the architectural registers 0 to L. Update units (U) sequentially, in program order, insert physical register identifiers PR(i) allocated to instructions I(i) with destination operands DOP(i) on bus lines denoted with the destination operands DOP(i). Source operands of an instruction I(i) may be renamed to physical register identifiers after physical register identifiers allocated to instructions older than I(i) are sequentially, in program order, inserted on the bus lines, but before physical register identifiers allocated to I(i) and younger instructions are inserted on the bus lines. A source operand SOP(i) is renamed to a physical register identifier that propagates on a bus line denoted with SOP(i).

Abstract: A renaming unit configured to rename source operands of instructions in a group. A renaming register maintains architectural to physical register mappings. Architectural to physical register mappings propagate from the renaming register through a chain of update units (U) over bus lines denoted with the architectural registers 0 to L. Update units (U) sequentially, in program order, insert physical register identifiers PR(i) allocated to instructions I(i) with destination operands DOP(i) on bus lines denoted with the destination operands DOP(i). Source operands of an instruction I(i) may be renamed to physical register identifiers after physical register identifiers allocated to instructions older than I(i) are sequentially, in program order, inserted on the bus lines, but before physical register identifiers allocated to I(i) and younger instructions are inserted on the bus lines. A source operand SOP(i) is renamed to a physical register identifier that propagates on a bus line denoted with SOP(i).

Abstract: A processor may include reservation stations to host instructions waiting to be issued to the execution units. Instructions in reservation stations comprise wrap bits and indexes, assigned by modulo counters. If wrap bits of two instructions are equal, then instruction with smaller index is older. If wrap bits of two instructions are different, then instruction with larger index is older. Responsive to exception event, wrap bit and index of an instruction executed with exception is compared with wrap bits and indexes of instructions in reservation stations to determine relative age. Instructions younger than the instruction executed with exception may be flushed from the reservation stations. Instructions in reservation stations may be grouped in pairs. In each pair, older ready instruction is selected using ready-to-issue bits, wrap bits, and indexes. Grouping and selecting instructions is repeated until one instruction remains. The remaining instruction is referred to as the oldest ready instruction.

Abstract: A renaming unit configured to rename source operands of instructions in a group of instructions. A RAT-like renaming register maintains architectural to physical register mappings from prior group of instructions. Physical registers from the renaming register propagate through a chain of update units (U) over bus lines. Bus lines comprise one bus line per architectural register. The chain of update units sequentially, in program order, inserts physical registers allocated to instructions in the group on bus lines that correspond to the destination operands. Source operands of an instruction may be renamed to physical registers after physical registers allocated to instructions older than said instruction are sequentially, in program order, inserted on the bus lines, but before physical registers allocated to said instruction and younger instructions are inserted on the bus lines. A source operand is renamed to a physical register on a bus line that corresponds to the source operand.

Abstract: A processor may include reservation stations to host instructions waiting to be issued to the execution units. Instructions in reservation stations comprise wrap bits and indexes, assigned by modulo counters. If wrap bits of two instructions are equal, then instruction with smaller index is older. If wrap bits of two instructions are different, then instruction with larger index is older. Responsive to exception event, wrap bit and index of an instruction executed with exception is compared with wrap bits and indexes of instructions in reservation stations to determine relative age. Instructions younger than the instruction executed with exception may be flushed from the reservation stations. Instructions in reservation stations may be grouped in pairs. In each pair, older ready instruction is selected using ready-to-issue bits, wrap bits, and indexes. Grouping and selecting instructions is repeated until one instruction remains. The remaining instruction is referred to as the oldest ready instruction.

Abstract: A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP.

Abstract: A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP.

Abstract: A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP.