Abstract: A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

Abstract: Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

Abstract: Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

Abstract: A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals.

Abstract: Enclosure services in a computer system having a Host computer and at least one Target device, are provided on a functional path, which is preferably a relatively high-speed, point-to-point serial bus between the Host computer and the at least one Target device. The at least one Target device and the Host computer each have a full power operational mode and an auxiliary power mode. The Host computer generates enclosure services commands and sends them to the at least one Target device on the functional path. The at least one Target device can receive and respond to the enclosure services commands, even when in the auxiliary power mode.

Abstract: A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

Abstract: A digital data waveform is precompensated for attenuation through a transmission medium. First, during actual initial power-on or upon reconfiguration of a digital communication system, attenuation characteristics of the transmission medium are actually measured. The attenuation characteristics can be measured by measuring the length of the transmission medium, measuring the error rate of test packets having known frequency, measuring the slope of a test pulse at two separate threshold voltages, and/or measuring the error rate of a random signal packet. Upon determination of the magnitude of the attenuation characteristic, one of a plurality of registers corresponding to the range of values of the attenuation characteristic is selected. These registers have a plurality of pre-emphasis coefficients to be applied in the driver to each bit of a series of digital signal pulses as determined by the transition history of at least three sequential bits.

Abstract: An echo cancellation circuit for neutralizing signal reflections in a differential link interface, and a method for achieving the same. The differential link interface includes a line driver that generates a line drive signal and a replica driver for generating a replica signal that mirrors the line drive signal within the differential link. The echo cancellation circuit includes a slope adjustment device within the replica driver for temporarily altering the slope of the replica line drive signal during a signal reflection at the output of the line driver, such that the amplitude of the replica signal corresponds to the amplitude of the line drive signal during the signal reflection.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) current mode differential link with precompensation is provided. The Complementary Metal Oxide Semiconductor (CMOS) bi-directional current mode differential link with precompensation includes a CMOS driver receiving a data input and having an output coupled to a transmission line. A CMOS replica driver receives the data input and provides a replica driver output substantially equal to the CMOS driver output. A CMOS receiver is coupled to both the transmission line and replica driver output. The CMOS receiver subtracts the replica driver output from a signal at the transmission line. The CMOS driver and the CMOS replica driver include a plurality of parallel current sources. Each of the current sources is arranged to send positive or negative current through a load responsive to an applied control signal. The use of the plurality of parallel current sources allows the CMOS driver to effectively implement precompensation.

Abstract: A digital data waveform precompensated for off-chip cable attenuation includes peaks with exponential tails at signal transitions. A driver output stage generating the waveform includes an output transistor pulling the output to a peak voltage level when an input goes high. After a delay, a transistor closes a feedback loop containing a resistive load, exponentially changing the voltage level of the output to a final voltage level. A complementary output transistor pulls the output to a ground voltage level when the input goes low, with a transistor closing a feedback loop containing a resistive load for exponential change of the output to a final voltage level. The separate resistive paths equalize the time constant of the exponential tails despite a difference in the gate capacitances of the output transistors. The received waveform after cable attenuation exhibits pulse shapes closer to the predefined pulse shapes on which a receiver is designed to operate.

Abstract: A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol.

Abstract: A full-duplex, differential, bi-directional communications link for simultaneously transmitting differential data between electronic devices is provided. Each transceiver coupled to the communications channel comprises a CMOS (Complementary Metal-Oxide Semiconductor) differential driver and receiver. The differential driver provides constant CMOS voltage sources for providing stable data signal transmission at reduced voltage levels. Voltage sources providing a data signal voltage different from the desired data signal voltage can be placed into a high impedance mode to allow the desired data signal voltage to be transmitted on the common line. The differential receiver includes self-biasing feedback circuitry to provide biasing voltages to the circuit while avoiding manufacturing difficulties associated with providing precise bias voltages. The complementary amplifier structure of the receiver provides an increased common mode noise tolerance.