Patents by Inventor Deleep R. Nair
Deleep R. Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9431289Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.Type: GrantFiled: June 17, 2015Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Christopher V. Baiocco, Michael P. Chudzik, Deleep R. Nair, Jay M. Shah
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Patent number: 9196707Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.Type: GrantFiled: November 6, 2013Date of Patent: November 24, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl J. Radens, Jay M. Shah
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Publication number: 20150287629Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.Type: ApplicationFiled: June 17, 2015Publication date: October 8, 2015Inventors: Christopher V. Baiocco, Michael P. Chudzik, Deleep R. Nair, Jay M. Shah
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Patent number: 9093495Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.Type: GrantFiled: January 3, 2012Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Christopher Vincent Baiocco, Michael P. Chudzik, Deleep R. Nair, Jay M. Shah
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Patent number: 9059211Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.Type: GrantFiled: October 3, 2011Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl J. Radens, Jay M. Shah
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Patent number: 8993402Abstract: A semiconductor structure including a body-contacted finFET device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a SOI substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate structure over the body region of the fin(s), forming a source region on one end of the fin(s), forming a drain region on the opposite end of the fin(s), replacing the sacrificial gate structure with a metal gate, and forming electrical contacts to the source, drain, metal gate, and body contact region. The method may further include forming a body contact fin contemporaneously with the finFET fins that is in contact with the body contact region, through which electrical contact to the body contact region is made.Type: GrantFiled: August 16, 2012Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Narasimhulu Kanike, Deleep R. Nair
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Patent number: 8853796Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.Type: GrantFiled: May 19, 2011Date of Patent: October 7, 2014Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
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Publication number: 20140065783Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.Type: ApplicationFiled: November 6, 2013Publication date: March 6, 2014Applicant: International Business Machines CorporationInventors: Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl J. Radens, Jay M. Shah
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Publication number: 20140048881Abstract: A semiconductor structure including a body-contacted finFET device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a SOI substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate structure over the body region of the fin(s), forming a source region on one end of the fin(s), forming a drain region on the opposite end of the fin(s), replacing the sacrificial gate structure with a metal gate, and forming electrical contacts to the source, drain, metal gate, and body contact region. The method may further include forming a body contact fin contemporaneously with the finFET fins that is in contact with the body contact region, through which electrical contact to the body contact region is made.Type: ApplicationFiled: August 16, 2012Publication date: February 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimhulu Kanike, Deleep R. Nair
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Patent number: 8623714Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.Type: GrantFiled: March 22, 2010Date of Patent: January 7, 2014Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
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Patent number: 8563394Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.Type: GrantFiled: April 11, 2011Date of Patent: October 22, 2013Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
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Publication number: 20130168780Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.Type: ApplicationFiled: January 3, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Vincent Baiocco, Michael P. Chudzik, Deleep R. Nair, Jay M. Shah
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Publication number: 20130082337Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.Type: ApplicationFiled: October 3, 2011Publication date: April 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl J. Radens, Jay M. Shah
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Publication number: 20120292719Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Young Way TEH, Michael V. AQUILINO, Arifuzzaman (Arif) SHEIKH, Yun Ling TAN, Hao ZHANG, Deleep R. NAIR, Jinghong H. (John) LI
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Patent number: 8298897Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: GrantFiled: March 23, 2012Date of Patent: October 30, 2012Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20120256268Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.Type: ApplicationFiled: April 11, 2011Publication date: October 11, 2012Applicants: GlobalFoundries, Inc., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
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Patent number: 8237197Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: GrantFiled: July 7, 2010Date of Patent: August 7, 2012Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20120190160Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: ApplicationFiled: March 23, 2012Publication date: July 26, 2012Applicants: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20120007145Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: ApplicationFiled: July 7, 2010Publication date: January 12, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20110227136Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD., CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee