Abstract: A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization. The method comprises subjecting a clock error signal to a first exponentially weighted moving average (EWMA) filter to generate a first output signal, where the first EWMA filter comprises a first gain element. And the method further comprises subjecting the first output signal to a second EWMA filter to generate a second output signal, where the second EWMA filter comprises a second gain element and the second EWMA filter is coupled with a feedback loop having a delay element and a summing junction.

Abstract: This invention provides a system, method and apparatus for facilitating handoffs from a first communication network to a second communication network, the first communication network and second communication network being heterogeneous with respect to each other. The system, method and apparatus may further include a contextual information server, which stores contextual elements corresponding to a user device and the operating environment of the user device, and a handoff decision function module that evaluates at least one of the contextual elements to determine whether to handoff user device communications from the first communication network to the second communication network.

Abstract: A method for dynamically adjusting jitter buffer size according to buffer fill dynamics is disclosed. In one embodiment, an upper threshold and lower threshold for the jitter buffer are identified, wherein the lower buffer threshold identifies a minimum desirable number of packets in the jitter buffer, and the upper buffer threshold identifies a maximum desirable number of packets in the jitter buffer. Operating characteristics of the jitter buffer are monitored to identify instances when the jitter buffer size falls below or exceeds the desired thresholds. When a threshold is crossed, the adaptive algorithm alters the playback offset time, by introducing or deleting packets into the transmission path, to allow the jitter buffer size to return to a desirable target size within the threshold boundaries.

Abstract: Disclosed is a rate-based multi-level Active Queue Management with drop precedence differentiation method and apparatus which uses traffic rate information for congestion control. Using a nonlinear fluid-flow model of Traffic Control Protocol, an integral controller in a closed-loop configuration with gain settings characterized for stable operation allows a matching of the aggregate rate of the active TCP connections to the available capacity. Further disclosed is a method for calculation of the regime of gains over which stable operation of a given network obtains. An enhancement of the basic algorithm provides the ability to drop low-precedence packets in preference to higher precedence packets. This approach allows for a rate-based AQM approach for application in a differentiated service environment.

Abstract: Disclosed is an Active Queue Management method and apparatus which uses traffic rate information for congestion control. Using a nonlinear fluid-flow model of Traffic Control Protocol, an integral controller in a closed loop configuration with gain settings characterized for stable operation allows a matching of the aggregate rate of the active TCP connections to the available capacity. Further disclosed is a method for calculation of the regime of gains for which stable operation of a given network obtains. This approach allows for capacity matching while maintaining minimal queue size and high link utilization.

Abstract: Disclosed is a queue based multi-level Active Queue Management with drop precedence differentiation method and apparatus which uses queue size information for congestion control. The method provides for a lower complexity in parameter configuration and greater ease of configuration over a wide range of network conditions. A key advantage is a greater ability to maintain stabilized network queues, thereby minimizing the occurrences of queue overflows and underflows, and providing high system utilization.

Abstract: Disclosed is an Active Queue Management method and apparatus which uses traffic rate information for congestion control. Using a nonlinear fluid-flow model of Traffic Control Protocol, a proportional controller in a closed loop configuration with gain settings characterized for stable operation allows a matching of the aggregate rate of the active TCP connections to the available capacity. Further disclosed is a method for calculation of the regime of gains for which stable operation of a given network obtains. This approach allows for capacity matching while maintaining minimal queue size and high link utilization.

Abstract: A traffic controller is provided which integrates black-box tests of unauthorized applications to extract application characteristics from associated Internet traffic, exploits the networking information learned by host clients, actively scans and controls hosts on the corporate network, and dynamically configures a corporate firewall to block traffic to and from critical application network elements. As a result, the traffic controller effectively manages unauthorized applications and their associated traffic in a corporate environment.

Abstract: Where a common network clock is available at both a TDM receiver and a TDM transmitter which communicate via a packet network, differential clock recovery can be accomplished by matching the number of service clock pulses in a network reference clock period at the transmitter and receiver. In one embodiment the transmitter need only send a counter value from a counter that is clocked and reset, respectively, by the service clock and network reference clock, thereby allowing use of different types of oscillators, both analog and digital, to be implemented at the transmitter and receiver. The technique is also general enough to be applied in a wide variety of packet networks including but not limited to IP, MPLS and Ethernet. In an alternative embodiment, a faster derived network clock fdnc drives both the transmitter and receiver counters, which in turn are reset, respectively by the slower transmitter service clock fsc and slower receiver service clock frc.

Abstract: The invention includes a technique for clock recovery in a network having master and slave clocks in respective Time Division Multiplexing (“TDM”) network segments which are interconnected by a non-TDM segment. Master clock timestamps are sent to the slave. The slave measures a master clock timestamp inter-arrival interval, and sends slave clock timestamps to the master. The master measures a slave clock timestamp inter-arrival interval, and sends that slave clock timestamp inter-arrival interval to the slave. The slave then calculates an error signal based at least in-part on the difference between the master clock timestamp inter-arrival interval and the slave clock timestamp inter-arrival interval, and employs the difference to recover the first service clock in the second TDM segment.

Abstract: A clock synchronization backup mechanism is disclosed for maintaining clock synchronization during periods of degraded synchronization. The clock synchronization backup mechanism includes a jitter buffer having a fill value at a given sample time which is compared with a threshold. When the jitter buffer fill value exceeds the threshold, a non-normal condition is registered and the local clock frequency is set to a combination of a long-term frequency setting plus a threshold sensitive frequency adjustment. The clock synchronization backup mechanism is particularly useful for overcoming residual errors accumulated due to temperature change, oscillator degradation, and a variety of other system perturbations problematical for clock synchronization mechanisms known in the art.

Abstract: A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components, to determine whether the performance of the PLL would be considered satisfactory. For example, PLL design software may determine whether a PLL would be sufficiently stable if it was to be created using the particular selected components given the required design specifications. Where the PLL does not meet particular behavior characteristics, the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL. Designed PLLs may be used for timestamp based clock synchronization.

Abstract: A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

Abstract: Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

Abstract: A method and apparatus for locating in a list of pre-defined codes, a longest code matching a given code. The method and apparatus involve producing a search mask encoding at least one portion of said given code and comparing the search mask to a search key having a Prefix Node Bit Array (PNBA) in which a bit is set active in at least one of a plurality of bit positions corresponding to possible bit combinations of bits in a bit string having a length equal to or less than the longest predefined code in the plurality of pre-defined codes and arranged by the lengths of possible bit combinations and by numeric values of the bit combinations, to identify a common active bit position in the search key and the search mask corresponding to one of the pre-defined codes having a length greater than all others of said pre-defined codes which correspond to common active bit positions.

Abstract: A rotator switch including more tandem buffers than inputs is disclosed. An input data conditioner formats data to be transferred from the multiple inputs to the tandem buffers. Excess tandem buffers allow data to be transferred from inputs to tandem buffers at a rate less than the rate at which data arrives at the inputs. Excess capacity of the switch fabric may be used to carry overhead, or slow the rate at which data is transferred to the switch fabric.