Patents by Inventor Delia Ristoiu

Delia Ristoiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901216
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Gouraud, Delia Ristoiu
  • Publication number: 20230005735
    Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Delia RISTOIU, Pierre BAR, Francois LEVERD
  • Patent number: 11469095
    Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 11, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Delia Ristoiu, Pierre Bar, Francois Leverd
  • Publication number: 20220028725
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal GOURAUD, Delia RISTOIU
  • Patent number: 11171034
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Gouraud, Delia Ristoiu
  • Patent number: 10770306
    Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Bar, Francois Leverd, Delia Ristoiu
  • Publication number: 20200211835
    Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.
    Type: Application
    Filed: December 10, 2019
    Publication date: July 2, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Delia RISTOIU, Pierre BAR, Francois LEVERD
  • Publication number: 20200203211
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 25, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal GOURAUD, Delia RISTOIU
  • Publication number: 20190214270
    Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 11, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre BAR, Francois LEVERD, Delia RISTOIU
  • Patent number: 10304775
    Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 28, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Delia Ristoiu
  • Patent number: 10128295
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Publication number: 20180211915
    Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
    Type: Application
    Filed: September 11, 2017
    Publication date: July 26, 2018
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Delia Ristoiu
  • Publication number: 20180158861
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 7, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Publication number: 20180076250
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Patent number: 9917126
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny