Abstract: A single-pass method for generating test patterns for sequential circuits operates upon an iterative array of time-frames representing the circuit. A mapping function is inserted at the end of each time-frame. Fault objects arriving at circuit next-state lines are mapped into good next-state fault objects and are placed onto corresponding present-state lines for a next time-frame. The good next-state mapping permits fault-propagation and path-enabling function size to be bounded by a size established during an initial time-frame. Path-enabling functions created during the initial time-frame are saved and are reused during subsequent time-frames. A search for test patterns continues from one time-frame to a next until a valid test pattern is found for each detectable fault.

Abstract: A method for an incremental behavioral validation of a digital design expressed in a hardware description language includes: receiving a design expressed in HDL code; providing a user interface permitting a designer to insert special comments into the received HDL code; using the special comments to identify testable parts of the design; creating a demonstration sequence for a testable part; performing a behavioral simulation of the testable part and applying the demonstration sequence at inputs of that part to drive the simulation; displaying the results of the simulation via the user interface by observing outputs of the simulated testable part, permitting the designer to determine whether the testable part implements the requirements of an informal specification; modifying the HDL design to correct designer identified failures; and selecting a next testable part and continuing until all testable parts correctly implement the designer's understanding of the informal specification.