Abstract: A multi-sectored, multiple access communication system provides for low-skew sector transceiver clocks by novelly utilizing a multi-tap digital Phase-Locked Loop (PLL) in the delay match circuitry of each transceiver to efficiently and inexpensively generate clock signals for each transceiver that are temporally aligned within acceptable limits of the other transceivers. The inventive system and method obviate the need for matching the lengths of all of the cables connecting the base station (“master sector equipment”) to the transceivers (“slave sector equipment”), and also reduces the power requirement as a byproduct.

Abstract: A Time Division Duplex (TDD), Code Division Multiple Access (CDMA) communication system includes a plurality of Customer Premises Equipment (CPE) and an Access Point (AP) that communicate through RF links. A CPE contains a receiver baseband subsystem and a transmitter baseband subsystem, and further contains receiver circuitry operable during a receive period for receiving an RF carrier from the AP and for deriving a receiver tracking signal that is indicative of a frequency and phase shift between the received RF carrier and a reference signal. The receiver circuitry further includes a frequency to phase accumulator (FPA) and a digital phase shifter (DPS) for correcting the frequency and phase of a receiver baseband signal by an amount and in a direction indicated by the receiver tracking signal.

Abstract: A method and apparatus for Time Division Duplex (TDD) synchronization of Access Points (APEs) uses the 1 pulse-per-second timing pulses of the Global Positioning System (GPS) and synchronization state machines for its Time Division Multiple Access (TDMA) structure. As a result, the present invention obviates the need for expensive voltage-controlled oscillators used by the prior art, and achieves stable timing accuracy within approximately 7.5 minutes, as opposed to the 12 to 24-hour period needed by prior art methods.

Abstract: A method and system for cooperative transmission power control in a communication system is provided. The method, operating within a system having a base station and at least on mobile station, includes the step of providing a power control data structure having memory fields indexed according to a predetermined parameter set. The next step retrieves from one of the memory fields a transmission power control value and adjusts a transmission power level of the mobile station according to the retrieved value.

Abstract: A system for fast forward error correction coding and decoding is provided. The system includes a transmitting device having a data source and a forward error correction (FEC) encoder. The FEC is coupled to the data source and is adapted to encode packetized data from the data source. A channelizer is coupled to the at least one FEC encoder and is adapted to interleave the FEC encoded packetized data among a plurality of communication channels. The system also includes a receiving device adapted to receive the plurality of communication channels. The receiving device includes a dechannelizer, adapted to de-interleave the plurality of communication channels and a FEC decoder to reconstituted the packetized data.

Abstract: A method and system for cooperative transmission power control in a communication system is provided. The method, operating within a system having a base station and at least on mobile station, includes the step of providing a power control data structure having memory fields indexed according to a predetermined parameter set. The next step retrieves from one of the memory fields a transmission power control value and adjusts a transmission power level of the mobile station according to the retrieved value.

Abstract: A multi-sectored, multiple access communication system provides for low-skew sector transceiver clocks by novelly utilizing a multi-tap digital Phase-Locked Loop (PLL) in the delay match circuitry of each transceiver to efficiently and inexpensively generate clock signals for each transceiver that are temporally aligned within acceptable limits of the other transceivers. The inventive system and method obviate the need for matching the lengths of all of the cables connecting the base station (“master sector equipment”) to the transceivers (“slave sector equipment”), and also reduces the power requirement as a byproduct.

Abstract: A system for fast forward error correction coding and decoding is provided. The system includes a transmitting device having a data source and a forward error correction (FEC) encoder. The FEC is coupled to the data source and is adapted to encode packetized data from the data source. A channelizer is coupled to the at least one FEC encoder and is adapted to interleave the FEC encoded packetized data among a plurality of communication channels. The system also includes a receiving device adapted to receive the plurality of communication channels. The receiving device includes a dechannelizer, adapted to de-interleave the plurality of communication channels and a FEC decoder to reconstituted the packetized data.

Abstract: A method and apparatus for Time Division Duplex (TDD) synchronization of Access Points (APEs) uses the 1 pulse-per-second timing pulses of the Global Positioning System (GPS) and synchronization state machines for its Time Division Multiple Access (TDMA) structure. As a result, the present invention obviates the need for expensive voltage-controlled oscillators used by the prior art, and achieves stable timing accuracy within approximately 7.5 minutes, as opposed to the 12 to 24-hour period needed by prior art methods.

Abstract: An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of "1" and "0" chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.