Abstract: The present disclosure provides a multi-queue multi-cluster task scheduling method and system. The method includes: constructing a training data set; training and optimizing a plurality of parallel deep neural networks (DNN) by using the training data set to obtain a plurality of trained and optimized parallel DNNs; setting a reward function, where the reward function minimizes the sum of a task delay and energy consumption by adjusting a reward value proportion of the task delay and a reward value proportion of the energy consumption; inputting a to-be-scheduled state space into the plurality of trained and optimized parallel DNNs to obtain a plurality of to-be-scheduled action decisions; determining an optimal action decision among the plurality of to-be-scheduled action decisions based on the reward function for output; and scheduling the plurality of task attribute groups to a plurality of clusters based on the optimal action decision.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

Abstract: Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.

Abstract: A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

Abstract: An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.

Abstract: A system includes a sampler, a receiver phase-locked loop circuit configured to provide one or more input clock signals, and a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler. The phase interpolation circuit further includes a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code, and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal, wherein the outputs of the first phase interpolator and second phase interpolator are configured to be merged.

Abstract: The present disclosure provides a multi-queue multi-cluster task scheduling method and system, and relates to the technical field of cloud computing. The method includes: constructing a training data set; training and optimizing a plurality of parallel deep neural networks (DNN) by using the training data set to obtain a plurality of trained and optimized parallel DNNs; setting a reward function, where the reward function minimizes the sum of a task delay and energy consumption by adjusting a reward value proportion of the task delay and a reward value proportion of the energy consumption; inputting a to-be-scheduled state space into the plurality of trained and optimized parallel DNNs to obtain a plurality of to-be-scheduled action decisions; determining an optimal action decision among the plurality of to-be-scheduled action decisions based on the reward function for output; and scheduling the plurality of task attribute groups to a plurality of clusters based on the optimal action decision.

Abstract: The edge-cloud collaboration platform for intelligent coking monitoring of cracking furnace tubes includes an edge layer and a cloud layer, which can store and analyze big data, propose suggestions on optimization and improvement, and feed the suggestions back to the edge layer. The edge layer includes an intelligent temperature measuring device for an outer surface of a cracking furnace tube and/or an ethylene DCS/data acquisition device; the cloud layer includes a cracking furnace safety warning device, an intelligent coking diagnosis and prediction device for a cracking furnace tube, a hybrid job scheduling device, a multi-workflow scheduling device, a virtualized resource scheduling device, and a virtual resource optimization device; and the intelligent temperature measuring device for an outer surface of a cracking furnace tube includes an identification device for furnace tube and overlapped tube, and an abnormal data detection device.

Abstract: The edge-cloud collaboration platform for intelligent coking monitoring of cracking furnace tubes includes an edge layer and a cloud layer, which can store and analyze big data, propose suggestions on optimization and improvement, and feed the suggestions back to the edge layer. The edge layer includes an intelligent temperature measuring device for an outer surface of a cracking furnace tube and/or an ethylene DCS/data acquisition device; the cloud layer includes a cracking furnace safety warning device, an intelligent coking diagnosis and prediction device for a cracking furnace tube, a hybrid job scheduling device, a multi-workflow scheduling device, a virtualized resource scheduling device, and a virtual resource optimization device; and the intelligent temperature measuring device for an outer surface of a cracking furnace tube includes an identification device for furnace tube and overlapped tube, and an abnormal data detection device.

Abstract: The present invention discloses a cooperative scheduling method and system for a computing resource and a network resource of a container cloud platform. The method includes: obtaining a load value of a container in a physical machine of a data center; calculating a load margin of a current container; if the load margin of the current container is less than 0, generating a first container sequence; if the load margin of the current container is greater than 0, obtaining a load value of a next container managed by a current physical machine, calculating a load margin of the next container, and updating the calculated load margin of the next container to the load margin of the current container. According to the method and the system of the present invention, resource utilization can be effectively improved.

Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.

Abstract: Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.

Abstract: The present invention discloses a cooperative scheduling method and system for a computing resource and a network resource of a container cloud platform. The method includes: obtaining a load value of a container in a physical machine of a data center; calculating a load margin of a current container; if the load margin of the current container is less than 0, generating a first container sequence; if the load margin of the current container is greater than 0, obtaining a load value of a next container managed by a current physical machine, calculating a load margin of the next container, and updating the calculated load margin of the next container to the load margin of the current container. According to the method and the system of the present invention, resource utilization can be effectively improved.