Patents by Inventor Delong Cui

Delong Cui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250141418
    Abstract: An amplifier includes a first transmission line from a first terminal to a second terminal. The first transmission line is characterized by a first characteristic impedance matched to a resistance of a source from which a first signal is coupled to the second terminal. The amplifier includes a first resistor with a first resistance and a second resistor with a second resistance coupled between the second terminal and a third terminal. The first resistance and the second resistance are adjustable to match an input impedance at the second terminal to the first characteristic impedance and to tune a gain of a second signal at the third terminal over the first signal at the second terminal. The amplifier includes a second transmission line from the third terminal to a third resistor with a third resistance, the second transmission line being characterized by a second characteristic impedance matched to the third resistance.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Inventors: Guansheng Li, Jerry Jifang Han, Bo Zhang, Delong Cui, Jun Cao
  • Publication number: 20250141482
    Abstract: In some implementations, the circuitry may include a circuit configured to receive a baseband signal, the baseband signal having an intermodulated non-linear distorted portion and a harmonic distorted portion. In addition, the circuitry may include a compensator coupled to the circuit, the compensator configured to generate a value to compensate for the intermodulated non-linear distorted portion without compensating for the harmonic distorted portion. The circuitry may include where the compensator is configured to output the value. The circuitry may include where the circuit is configured to adjust the baseband signal using the value. In some embodiments, the baseband signal can be baseband voltage. In some embodiments, the value can be a complex number.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Xiaochen Yang, Yong Liu, Renfei Liu, Chifeng Wang, Delong Cui, Jun Cao
  • Publication number: 20250141435
    Abstract: In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Delong Cui, Guansheng Li, Jun Cao, Yonghyun Shim, Yu-Ming Ying
  • Publication number: 20250141464
    Abstract: A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Chang Liu, Boyu Hu, Xiaoliang Li, Delong Cui, Jun Cao
  • Patent number: 12283930
    Abstract: Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: April 22, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Guansheng Li, Heng Zhang, Delong Cui, Jun Cao
  • Patent number: 12212334
    Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: January 28, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
  • Publication number: 20240413827
    Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Yonghyun Shim, YU-Ming Ying, Guansheng Li, Delong Cui, Jun Cao
  • Patent number: 12107573
    Abstract: A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 1, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Guansheng Li, Delong Cui, Jun Cao
  • Publication number: 20240154591
    Abstract: An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.
    Type: Application
    Filed: June 15, 2023
    Publication date: May 9, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Jiawen Zhang, Delong Cui, Afshin Momtaz, Kun Chuai, Jun Cao
  • Patent number: 11954526
    Abstract: The present disclosure provides a multi-queue multi-cluster task scheduling method and system. The method includes: constructing a training data set; training and optimizing a plurality of parallel deep neural networks (DNN) by using the training data set to obtain a plurality of trained and optimized parallel DNNs; setting a reward function, where the reward function minimizes the sum of a task delay and energy consumption by adjusting a reward value proportion of the task delay and a reward value proportion of the energy consumption; inputting a to-be-scheduled state space into the plurality of trained and optimized parallel DNNs to obtain a plurality of to-be-scheduled action decisions; determining an optimal action decision among the plurality of to-be-scheduled action decisions based on the reward function for output; and scheduling the plurality of task attribute groups to a plurality of clusters based on the optimal action decision.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 9, 2024
    Assignee: GUANGDONG UNIVERSITY OF PETROCHEMICAL TECHNOLOGY
    Inventors: Delong Cui, Jianpeng Lin, Zhiping Peng, Qirui Li, Jieguang He, Jinbo Qiu
  • Publication number: 20240097692
    Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
  • Patent number: 11929756
    Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: March 12, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Yong Liu, Jun Cao, Delong Cui
  • Patent number: 11916561
    Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: February 27, 2024
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Boyu Hu, Chang Liu, Guansheng Li, Haitao Wang, Delong Cui, Jun Cao
  • Patent number: 11863198
    Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: January 2, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
  • Publication number: 20230353173
    Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Xiaochen Yang, Hamid Hatamkhani, Guansheng Li, Yong Liu, Delong Cui, Jun Cao
  • Publication number: 20230327623
    Abstract: Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Guansheng Li, Heng Zhang, Delong Cui, Jun Cao
  • Publication number: 20230327663
    Abstract: A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Inventors: Guansheng Li, Delong Cui, Jun Cao
  • Publication number: 20230299785
    Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
  • Publication number: 20230299781
    Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
  • Publication number: 20230291411
    Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Inventors: Yong Liu, Jun Cao, Delong Cui