Abstract: An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

Abstract: An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

Abstract: A circuit including a first resistor, a second resistor, a current source and a transistor. The first resistor is between a voltage rail and a drive interconnect. The drive interconnect and the voltage rail are electrically connected to the first resistor. The second resistor is between the drive interconnect and ground. Ground and the drive interconnect are electrically connected to the second resistor. The current source is between the voltage rail and the drive interconnect. The drive interconnect and the voltage rail are electrically connected to the current source. The transistor is between the drive interconnect and a sink interconnect. The drive interconnect and the sink interconnect are electrically connected to the transistor.

Abstract: A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

Abstract: The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

Abstract: An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

Abstract: A reference buffer with wide output voltage and current range is provided. A reference buffer includes an error amplifier comprising a first input, a second input, and a first output, wherein the amplifier is configured to generate an output signal indicative of an error between an output reference signal and an internal reference signal. The reference buffer further includes a first voltage follower circuit configured to generate the output reference signal based, at least in part, on the output signal of the error amplifier, wherein the first voltage follower comprises a third input and a second output, and wherein the second output is coupled to the second input of the error amplifier.

Abstract: An electronic circuit including an amplifier, a first variable capacitance and a second variable capacitance. The amplifier receives an input signal across an inverting input terminal of the amplifier and a non-inverting input terminal of the amplifier. The first variable capacitance is electrically directly connected to the output terminal of the amplifier and the inverting input terminal of the amplifier. The second variable capacitance is electrically directly connected to the output terminal of the amplifier and the non-inverting input terminal of the amplifier.

Abstract: A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k?1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

Abstract: An example amplifier includes a first transconductance circuit, which includes a first output coupled to a first current source, a first input, a first network, and a cascode circuit; and a second transconductance circuit, which includes a second output coupled to a second input and a second current source; wherein the first current source is coupled to a supply voltage and the second current source is coupled to an electrical ground; and wherein the first output is coupled to the second output.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: An example data path to a receiver includes: an analog front-end circuit (AFE) configured to receive a first voltage supply; a first circuit coupled to an output of the AFE, the first circuit including: a first buffer having an input coupled to the output of the AFE; a second buffer; a first switch coupled between an output of the first buffer and an input of the second buffer; and a second switch coupled between an output of the second buffer and an input of an ADC of the receiver; wherein the first buffer is configured to receive the first voltage supply, the second buffer is configured to receive a second voltage supply, and the ADC is configured to receive a third voltage supply less than the first voltage supply.

Abstract: An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

Abstract: A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

Abstract: Systems and methods are related to device including but not limited to a SAR ADC. The device includes a first digital to analog conversion (DAC) circuit including first capacitors. The digital to analog conversion (DAC) circuit is configured to adjust a first input voltage in response to a first control signal. The device also includes a first comparator configured to receive an adjusted input voltage from the digital to analog conversion (DAC) circuit. The first control signal is provided in response to a target input voltage and a sensed input voltage and adjusts the first input voltage using the first capacitors.

Abstract: A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency, and a second clock signal having a second frequency. A control logic is configured to generate the control signal, based, at least in part, on the second clock signal, and two or more analog to digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, wherein the multiplexer is configured to select a set of the second number of inputs to be output, wherein the set of the second number of inputs selected is based, at least in part, on a control signal. The apparatus includes one or more unit-ADCs, wherein the respective outputs of the one or more unit-ADCs are coupled to the multiplexer as an input.

Abstract: An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

Abstract: A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k?1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

Abstract: A reference buffer with wide output voltage and current range is provided. A reference buffer includes an error amplifier comprising a first input, a second input, and a first output, wherein the amplifier is configured to generate an output signal indicative of an error between an output reference signal and an internal reference signal. The reference buffer further includes a first voltage follower circuit configured to generate the output reference signal based, at least in part, on the output signal of the error amplifier, wherein the first voltage follower comprises a third input and a second output, and wherein the second output is coupled to the second input of the error amplifier.

Abstract: An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.