Abstract: A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.

Abstract: An alignment fixture for use in sealing integrated circuit packages including a body having rectangular alignment cavities therein for receiving components of integrated circuit packages. The body is inclined at an angle relative to a horizontal reference plane. The rectangular alignment cavities are rotated at 451/2 angle relative to a longitudinal axis of the body.

Abstract: Silicon is used to create multi-chip carriers for integrated circuits. The process of fabricating the carriers uses standard integrated circuit fabrication equipment. Cavities are etched into a silicon wafer, metallization or polysilicon is deposited to electrically interconnect the cavities, and integrated circuit die are placed in the cavities. Traces connecting the integrated circuits are buried in channels formed in the silicon, which can be doped and biased to provide enhanced isolation between traces as well as control over the electrical characteristics of the traces. The traces can be formed in multiple layers of material placed on the wafer to provide additional communication capacity in the carriers.

Abstract: A ceramic chip carrier package for integrated circuits is described which provides reduced interlead capacitance. A cavity for the placement of the integrated circuit chip is centrally located on a substrate. The leads of the package are bridged between the cavity and the outer periphery of the substrate. The leads are bonded to the substrate using adhesive glass placed on the substrate at the outer periphery of the cavity and at the outer periphery of the substrate. Sealing glass is placed on the outer periphery of the substrate over the leads to provide a bonding material for a lid to the package. The area between the cavity and the outer periphery of the substrate has no adhesive or sealing glass which thus provides an air dielectric between the leads so that interlead capacitance is reduced.

Abstract: An integrated circuit chip carrier having reduced and predicable interlead capacitance, reduced glass chip formation, and improved wirebonding characteristics is disclosed. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.

Abstract: Improved performance and reliability is obtained in test sockets for integrated circuits (ICs). Sufficient over-travel is provided to prevent pinching when the IC and its carrier are inserted in the test socket and the lid is latched closed. A power operated piston applies controllable and uniform pressure to force the IC leads onto contact pins in the test socket base. This controllable and uniform pressure prevents gouged IC leads, bent test socket pins, and other damage that prevents proper electrical and mechanical contact between IC leads and contact pins resulting in erroneous indications of faulty IC operation.

Abstract: An organization of serial-parallel-serial (SPS) charged-coupled-device (CCD) memory arrays or blocks into a memory system is disclosed. Each memory block is comprised of an N-bit input register, an N-bit output register, N S-bit parallel registers and an N-bit I/O register. Data is bit-serially entered into the input register at a frequency F.sub.0 is bit-parallelly shifted through the parallel registers and simultaneously into the output register and the I/O register at a frequency F.sub.0 /N. Addressed read data are captured by the I/O register and are circulated continuously therein independently of the recirculation process performed by the output register, input register such that if I/O transfer rates are lower than the allowable refresh frequency of the charged-coupled-devices of the memory block, and if one or more refresh cycles are utilized, the addressed read data always remains available in the I/O register.