Patents by Inventor Demetrio Pellicone
Demetrio Pellicone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9984756Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: August 31, 2017Date of Patent: May 29, 2018Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20170365345Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: August 31, 2017Publication date: December 21, 2017Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 9779821Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: April 24, 2017Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20170229183Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 9632730Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: March 7, 2016Date of Patent: April 25, 2017Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20160188259Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 9281064Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: February 26, 2015Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20150170745Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: February 26, 2015Publication date: June 18, 2015Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8982627Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: November 11, 2013Date of Patent: March 17, 2015Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20140071767Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: November 11, 2013Publication date: March 13, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8582364Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: June 7, 2011Date of Patent: November 12, 2013Assignee: Micron Technology, Inc.Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20110235411Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8018771Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: May 19, 2008Date of Patent: September 13, 2011Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 7793031Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.Type: GrantFiled: September 8, 2006Date of Patent: September 7, 2010Inventors: Laura Sartori, Adamo Corsi, Marco Roveda, Giuseppe Maurizio Lorusso, Daniela Ruggeri, Demetrio Pellicone
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Publication number: 20100039858Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: May 19, 2008Publication date: February 18, 2010Applicant: STMicroelectronics S.r.l.Inventors: Marco MACCARRONE, Giuseppe GIANNINI, Demetrio PELLICONE
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Patent number: 7571362Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.Type: GrantFiled: November 8, 2006Date of Patent: August 4, 2009Inventors: Demetrio Pellicone, Adamo Corsi, Marco Roveda, Concetta Di Tuoro, Procolo Carannante, Gianfranco Ferrante
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Publication number: 20070115743Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.Type: ApplicationFiled: September 8, 2006Publication date: May 24, 2007Applicant: STMicroelectronics S.r.I.Inventors: Laura Sartori, Adamo Corsi, Marco Roveda, Giuseppe Lorusso, Daniela Ruggeri, Demetrio Pellicone
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Publication number: 20070109856Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells.Type: ApplicationFiled: November 8, 2006Publication date: May 17, 2007Applicant: STMicroelectronics S.r.IInventors: Demetrio Pellicone, Adamo Corsi, Marco Roveda, Concetta Di Tuoro, Procolo Carannante, Gianfranco Ferrante