Abstract: A netlist is updated based on an engineering change order (ECO) circuit network by determining primary cuts of a first network of a netlist and secondary cuts of the ECO circuit network. The primary cuts are at least a portion of the first network, and include one or more logic elements and an output node. The secondary cuts are a least a portion of the ECO circuit network, and include one or more logic elements and an output node. Further, matching cuts are determined from the primary cuts and the secondary cuts. The matching cuts include a first cut of the primary cuts and a second cut of the secondary cuts. A downward frontier of the ECO circuit network is determined from the matching cuts, and the netlist is updated based on the downward frontier.

Abstract: A method and apparatus for determining equivalence between two integrated circuit device designs. Functional blocks and compare points within a first design are compared with functional blocks and compare points in a second design to determine compare points that are matched. The integrated circuit designs are traversed net-wise and cut points are inserted at compare points that are matched and that are not determined to be constant. As each design is traversed, the design is flattened such that flat copies of both integrated circuit designs are obtained (that include the inserted cut points). The flat copies of the integrated circuit designs are then compared to determine equivalence.

Abstract: A system and method for generating gate level descriptions tables from simulation for formal verification. Implementation libraries contain table-based descriptions of user defined primitives (UDPs), various-strength primitives, hierarchical structural cells and non-functional constructs, such as timing and simulation assertion checks. In order to use the library cells for use by test-generation (ATPG) and formal verification (FV), the present invention provides a library reader and a model builder that read in the library cells and construct gate-level models usable by ATPG processes. The present invention also provides a translator that accesses the ATPG models through an API (Application Programming Interface) interface and produces FV models that are usable by FV processes. Significantly, according to the present invention, the FV models are generated based on the ATPG models. Library cell complexities that would require different ATPG and FV models are automatically detected.