Patents by Inventor Deng-Shun Chang

Deng-Shun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ESD protection for high voltage applications
    Patent number: 7563653
    Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: July 21, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jian-Hsing Lee, Deng-Shun Chang
  • Electrostatic discharge protection device
    Patent number: 7485905
    Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: February 3, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Chi Hung, Jian-Hsing Lee, Hung-Lin Chen, Deng-Shun Chang
  • ESD PROTECTION FOR HIGH VOLTAGE APPLICATIONS
    Publication number: 20080233686
    Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.
    Type: Application
    Filed: May 1, 2008
    Publication date: September 25, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hsing LEE, Deng-Shun Chang
  • ESD protection for high voltage applications
    Patent number: 7385252
    Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: June 10, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hsing Lee, Deng-Shun Chang
  • ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    Publication number: 20080023766
    Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Chi Hung, Jian-Hsing Lee, Hung-Lin Chen, Deng-Shun Chang
  • ESD protection for high voltage applications
    Publication number: 20060065931
    Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.
    Type: Application
    Filed: September 27, 2004
    Publication date: March 30, 2006
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., Anpec Electronics Corporation
    Inventors: Jian-Hsing Lee, Deng-Shun Chang
  • Guard ring structure with deep N well on ESD devices
    Patent number: 6274909
    Abstract: In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 14, 2001
    Assignee: Etron Technology, Inc.
    Inventors: Kun-Zen Chang, Deng-Shun Chang, Rong-Tai Kao